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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit 7da92c0f authored by Marek Gumiński's avatar Marek Gumiński
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Enabled TRU, TATSU and PSU

parent 6a520ac7
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Showing with 4 additions and 2 deletions
top/scb_18ports/scb_top_synthesis.vhd
View file @ 7da92c0f
......@@ -295,6 +295,7 @@ architecture Behavioral of scb_top_synthesis is
g_with_PSTATS : boolean;
g_with_muxed_CS : boolean;
g_with_watchdog : boolean;
g_with_PSU : boolean;
g_inj_per_EP : std_logic_vector(17 downto 0));
port (
sys_rst_n_i : in std_logic;
......@@ -780,12 +781,13 @@ phys: entity work.gtwizard_ultrascale_1
g_num_ports => c_NUM_PORTS,
g_simulation => g_simulation,
g_without_network => false,
g_with_TRU => false,
g_with_TATSU => false,
g_with_TRU => true,
g_with_TATSU => true,
g_with_HWIU => true,
g_with_PSTATS => true,
g_with_muxed_CS => false,
g_with_watchdog => true,
g_with_PSU => true,
g_inj_per_EP => "00" & x"0000")
port map (
sys_rst_n_i => sys_rst_n_i,
......
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