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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit 48a8fedd authored by Marek Gumiński's avatar Marek Gumiński
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Added missing clock and reset signals in top module.

parent 95211a73
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Showing with 7 additions and 13 deletions
top/scb_18ports/scb_top_synthesis.vhd
View file @ 48a8fedd
......@@ -164,7 +164,7 @@ entity scb_top_synthesis is
mbl_scl_b : inout std_logic_vector(1 downto 0);
mbl_sda_b : inout std_logic_vector(1 downto 0);
sensors_scl_b: inout std_logic;
sensors_scl_b: inout std_logic;
sensors_sda_b: inout std_logic;
mb_fan1_pwm_o : out std_logic;
......@@ -618,7 +618,8 @@ begin
--not sure if it shouldn't be swapped
to_phys_tx_k(8*(i+1)-1 downto 8*i) <= to_phys(i).tx_k;
from_phys(i).ref_clk <= clk_ref;
from_phys(i).rx_clk <= rxusrclk2(i);
from_phys(i).rx_data <= from_phys_rx_data(64*(i+1)-1 downto 64*i);
......@@ -640,7 +641,7 @@ begin
-- phy_rdy is asserted when tx and rx are active
-- (incompatible with WR)
from_phys(i).rdy <= phy_rdy(i);
from_phys(i).rdy <= tx_active and rx_active;
-- reset sync
sync_tx_rst_sp : process (txusrclk2(i))
......@@ -650,15 +651,8 @@ begin
end if;
end process sync_tx_rst_sp;
-- phy ready sync
sync_phy_rdy_sp : process (rxusrclk2(i))
begin
if (rising_edge(rxusrclk2(i))) then
phy_rdy(i) <= tx_active and rx_active;
end if;
end process sync_phy_rdy_sp;
end generate;
--clock buffers for rx clock
genbufg : for i in 0 to c_NUM_PHYS-1 generate
U_RX_Clock_Buffer : BUFG_GT port map
......@@ -709,8 +703,8 @@ port map(
gtwiz_reset_rx_datapath_in => (others => '0'),
gtwiz_reset_rx_cdr_stable_out => open,
gtwiz_reset_tx_done_out => open,
gtwiz_reset_rx_done_out => open,
gtwiz_reset_tx_done_out(0) => tx_active,
gtwiz_reset_rx_done_out(0) => rx_active,
gtwiz_userdata_tx_in => to_phys_tx_data,
gtwiz_userdata_rx_out => from_phys_rx_data,
......
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