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Resource Evaluation of WR switch HDL for Ultrascale Plus
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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commits
500d1f1a
Commit
500d1f1a
authored
Sep 04, 2019
by
Marek Gumiński
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Changed the way that wrf is resized for PSU
parent
b7403bcc
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6 changed files
with
27 additions
and
27 deletions
+27
-27
wr_fabric_pkg.vhd
ip_cores/wr-cores-local/modules/fabric/wr_fabric_pkg.vhd
+9
-9
xwrf_reg.vhd
ip_cores/wr-cores-local/modules/fabric/xwrf_reg.vhd
+4
-4
psu_announce_snooper.vhd
modules/wrsw_psu/psu_announce_snooper.vhd
+2
-2
psu_packet_injection.vhd
modules/wrsw_psu/psu_packet_injection.vhd
+3
-3
psu_pkg.vhd
modules/wrsw_psu/psu_pkg.vhd
+4
-4
xwrsw_psu.vhd
modules/wrsw_psu/xwrsw_psu.vhd
+5
-5
No files found.
ip_cores/wr-cores-local/modules/fabric/wr_fabric_pkg.vhd
View file @
500d1f1a
...
...
@@ -57,16 +57,16 @@ package wr_fabric_pkg is
type
t_wrf_source_out
is
record
adr
:
std_logic_vector
(
1
downto
0
);
dat
:
std_logic_vector
(
15
downto
0
);
dat
:
std_logic_vector
(
63
downto
0
);
cyc
:
std_logic
;
stb
:
std_logic
;
we
:
std_logic
;
sel
:
std_logic_vector
(
1
downto
0
);
end
record
;
type
t_wrf_source
64
_out
is
record
type
t_wrf_source
16
_out
is
record
adr
:
std_logic_vector
(
1
downto
0
);
dat
:
std_logic_vector
(
63
downto
0
);
dat
:
std_logic_vector
(
15
downto
0
);
cyc
:
std_logic
;
stb
:
std_logic
;
we
:
std_logic
;
...
...
@@ -91,12 +91,12 @@ package wr_fabric_pkg is
end
record
;
subtype
t_wrf_sink_in
is
t_wrf_source_out
;
subtype
t_wrf_sink
64_in
is
t_wrf_source64
_out
;
subtype
t_wrf_sink
16_in
is
t_wrf_source16
_out
;
subtype
t_wrf_sink_out
is
t_wrf_source_in
;
type
t_wrf_source_in_array
is
array
(
natural
range
<>
)
of
t_wrf_source_in
;
type
t_wrf_source_out_array
is
array
(
natural
range
<>
)
of
t_wrf_source_out
;
type
t_wrf_source
64_out_array
is
array
(
natural
range
<>
)
of
t_wrf_source64
_out
;
type
t_wrf_source
16_out_array
is
array
(
natural
range
<>
)
of
t_wrf_source16
_out
;
subtype
t_wrf_sink_in_array
is
t_wrf_source_out_array
;
subtype
t_wrf_sink_out_array
is
t_wrf_source_in_array
;
...
...
@@ -110,9 +110,9 @@ package wr_fabric_pkg is
constant
c_dummy_src_in
:
t_wrf_source_in
:
=
(
'0'
,
'0'
,
'0'
,
'0'
);
constant
c_dummy_snk_in
:
t_wrf_sink_in
:
=
(
"XX"
,
"XXXXXXXXXXXXXXXX"
,
'0'
,
'0'
,
'0'
,
"XX"
);
constant
c_dummy_snk64_in
:
t_wrf_sink64_in
:
=
(
"XX"
,
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"
,
'0'
,
'0'
,
'0'
,
"XX"
);
constant
c_dummy_snk16_in
:
t_wrf_sink16_in
:
=
(
"XX"
,
"XXXXXXXXXXXXXXXX"
,
'0'
,
'0'
,
'0'
,
"XX"
);
-----------------------------------------------------------------------------
...
...
@@ -146,10 +146,10 @@ package wr_fabric_pkg is
port
(
rst_n_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
snk_i
:
in
t_wrf_sink
64
_in
;
snk_i
:
in
t_wrf_sink_in
;
snk_o
:
out
t_wrf_sink_out
;
src_i
:
in
t_wrf_source_in
;
src_o
:
out
t_wrf_source
64
_out
);
src_o
:
out
t_wrf_source_out
);
end
component
;
component
xwrf_loopback
...
...
ip_cores/wr-cores-local/modules/fabric/xwrf_reg.vhd
View file @
500d1f1a
...
...
@@ -40,16 +40,16 @@ entity xwrf_reg is
port
(
rst_n_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
snk_i
:
in
t_wrf_sink
64
_in
;
snk_i
:
in
t_wrf_sink_in
;
snk_o
:
out
t_wrf_sink_out
;
src_i
:
in
t_wrf_source_in
;
src_o
:
out
t_wrf_source
64
_out
);
src_o
:
out
t_wrf_source_out
);
end
xwrf_reg
;
architecture
behav
of
xwrf_reg
is
type
t_reg_fsm
is
(
PASS
,
STALL
,
FLUSH
);
signal
state
:
t_reg_fsm
;
signal
temp
:
t_wrf_sink
64
_in
;
signal
temp
:
t_wrf_sink_in
;
begin
process
(
clk_i
)
...
...
@@ -64,7 +64,7 @@ begin
if
rising_edge
(
clk_i
)
then
if
(
rst_n_i
=
'0'
)
then
state
<=
PASS
;
src_o
<=
c_dummy_snk
64
_in
;
src_o
<=
c_dummy_snk_in
;
else
case
state
is
when
PASS
=>
...
...
modules/wrsw_psu/psu_announce_snooper.vhd
View file @
500d1f1a
...
...
@@ -84,11 +84,11 @@ entity psu_announce_snooper is
rst_n_i
:
in
std_logic
;
-- interface with NIC
snk_i
:
in
t_wrf_sink
64
_in
;
snk_i
:
in
t_wrf_sink_in
;
snk_o
:
out
t_wrf_sink_out
;
src_i
:
in
t_wrf_source_in
;
src_o
:
out
t_wrf_source
64
_out
;
src_o
:
out
t_wrf_source_out
;
rtu_dst_port_mask_i
:
in
std_logic_vector
(
g_port_number
-1
downto
0
);
...
...
modules/wrsw_psu/psu_packet_injection.vhd
View file @
500d1f1a
...
...
@@ -68,9 +68,9 @@ entity psu_packet_injection is
src_i
:
in
t_wrf_source_in
;
src_o
:
out
t_wrf_source
64
_out
;
src_o
:
out
t_wrf_source_out
;
snk_i
:
in
t_wrf_sink
64
_in
;
snk_i
:
in
t_wrf_sink_in
;
snk_o
:
out
t_wrf_sink_out
;
rtu_dst_port_mask_o
:
out
std_logic_vector
(
g_port_number
-1
downto
0
);
...
...
@@ -110,7 +110,7 @@ architecture rtl of psu_packet_injection is
signal
within_packet
:
std_logic
;
signal
select_inject
:
std_logic
;
signal
inj_src
:
t_wrf_source
64
_out
;
signal
inj_src
:
t_wrf_source_out
;
signal
inj_snk
:
t_wrf_sink_out
;
signal
inj_stb
:
std_logic
;
signal
inject_req_latched
:
std_logic
;
...
...
modules/wrsw_psu/psu_pkg.vhd
View file @
500d1f1a
...
...
@@ -70,11 +70,11 @@ package psu_pkg is
clk_sys_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
snk_i
:
in
t_wrf_sink
64
_in
;
snk_i
:
in
t_wrf_sink_in
;
snk_o
:
out
t_wrf_sink_out
;
src_i
:
in
t_wrf_source_in
;
src_o
:
out
t_wrf_source
64
_out
;
src_o
:
out
t_wrf_source_out
;
rtu_dst_port_mask_i
:
in
std_logic_vector
(
g_port_number
-1
downto
0
);
holdover_on_i
:
in
std_logic
;
...
...
@@ -101,8 +101,8 @@ package psu_pkg is
src_i
:
in
t_wrf_source_in
;
src_o
:
out
t_wrf_source
64
_out
;
snk_i
:
in
t_wrf_sink
64
_in
;
src_o
:
out
t_wrf_source_out
;
snk_i
:
in
t_wrf_sink_in
;
snk_o
:
out
t_wrf_sink_out
;
rtu_dst_port_mask_o
:
out
std_logic_vector
(
g_port_number
-1
downto
0
);
rtu_prio_o
:
out
std_logic_vector
(
2
downto
0
);
...
...
modules/wrsw_psu/xwrsw_psu.vhd
View file @
500d1f1a
...
...
@@ -127,7 +127,7 @@ entity xwrsw_psu is
rst_n_i
:
in
std_logic
;
-- interface with NIC: tx path
tx_snk_i
:
in
t_wrf_sink
64
_in
;
tx_snk_i
:
in
t_wrf_sink_in
;
tx_snk_o
:
out
t_wrf_sink_out
;
tx_rtu_dst_port_mask_i
:
in
std_logic_vector
(
g_port_mask_bits
-1
downto
0
);
tx_rtu_prio_i
:
in
std_logic_vector
(
2
downto
0
);
...
...
@@ -137,11 +137,11 @@ entity xwrsw_psu is
-- interface with NIC: rx path
rx_src_i
:
in
t_wrf_source_in
;
rx_src_o
:
out
t_wrf_source
64
_out
;
rx_src_o
:
out
t_wrf_source_out
;
-- interface with RTU/SWcore: tx path
tx_src_i
:
in
t_wrf_source_in
;
tx_src_o
:
out
t_wrf_source
64
_out
;
tx_src_o
:
out
t_wrf_source_out
;
tx_rtu_dst_port_mask_o
:
out
std_logic_vector
(
g_port_mask_bits
-1
downto
0
);
tx_rtu_prio_o
:
out
std_logic_vector
(
2
downto
0
);
tx_rtu_drop_o
:
out
std_logic
;
...
...
@@ -149,7 +149,7 @@ entity xwrsw_psu is
tx_rtu_rsp_ack_i
:
in
std_logic
;
-- interface with SWcore: rx path
rx_snk_i
:
in
t_wrf_sink
64
_in
;
rx_snk_i
:
in
t_wrf_sink_in
;
rx_snk_o
:
out
t_wrf_sink_out
;
-- communciation with rt_subsystem
...
...
@@ -197,7 +197,7 @@ architecture behavioral of xwrsw_psu is
signal
rx_rd_ram_data
:
std_logic_vector
(
65
downto
0
);
signal
tx_src_in
:
t_wrf_source_in
;
signal
tx_src_out
:
t_wrf_source
64
_out
;
signal
tx_src_out
:
t_wrf_source_out
;
signal
inject_req
:
std_logic
;
signal
inject_ready
:
std_logic
;
...
...
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