Fixed a non static assignment.

It caused a warning.

Fixed a non static assignment.
It caused a warning.
6b578c8d · Marek Gumiński · a25f7c8f · 6b578c8d
Commit 6b578c8d authored Aug 21, 2019 by Marek Gumiński
Hide whitespace changes
Inline Side-by-side

Showing with 5 additions and 2 deletions

swc_rd_wr_ram.vhd modules/wrsw_swcore/ram_bug/swc_rd_wr_ram.vhd +5 -2

No files found.
--- a/modules/wrsw_swcore/ram_bug/swc_rd_wr_ram.vhd
+++ b/modules/wrsw_swcore/ram_bug/swc_rd_wr_ram.vhd
@@ -66,12 +66,15 @@ end swc_rd_wr_ram;
 architecture rtl of swc_rd_wr_ram is

  signal rstb   : std_logic;
+  signal wen    : std_logic_vector(g_data_width/8-1 downto 0);

 begin  -- rtl
  
+  wen     <= (others => we_i);
+  
 -- xpm_memory_sdpram: Simple Dual Port RAM
 -- Xilinx Parameterized Macro, Version 2017.4
-xpm_memory_sdpram_inst : xpm_memory_sdpram
+  xpm_memory_sdpram_inst : xpm_memory_sdpram
  generic map (

    -- Common module generics
@@ -113,7 +116,7 @@ xpm_memory_sdpram_inst : xpm_memory_sdpram
    -- Port A module ports
    clka                    => clk_i,
    ena                     => '1',
-    wea                     => (others => we_i),
+    wea                     => wen,
    addra                   => wa_i,
    dina                    => wd_i,
    injectsbiterra          => '0',