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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit 7929904a authored by Marek Gumiński's avatar Marek Gumiński
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Creotech Instruments S.A. \hspace{15pt} tel. +48 22 233 10 27 \\
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05-500 Piaseczno, Poland \hspace{23pt} www.creotech.pl
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\documentclass[12pt,a4paper,final,titlepage]{article}
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\newcommand{\CtiDocumentTitle}{WRS resource utilisation }
\newcommand{\CtiHeader}{Evaluation of WRS firmware resource utilisation}
\newcommand{\CtiSubtitle}{on Xilinx US+ FPGA}
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\section{Introduction}
Presented report summarizes evaluation of White Rabbit Switch (WRS) firmware resource evaluation. Firmware is evaluated for Xilinx Zynq UltraScale+ (US+) MPSoC XCZU11EG-1FFVC1156E \ref{fig:fpga_over}.
\begin{figure}[h]
\caption{US+ FPGA family resource overview (\href{https://www.xilinx.com/support/documentation/data_sheets/ds891-zynq-ultrascale-plus-overview.pdf}{DS891}).}
\label{fig:fpga_over}
\includegraphics[scale=.65]{images/fpga_over_edit.pdf}
\end{figure}
The firmware was supposed to be tested in following configurations:
\begin{enumerate}
\item 1G Ethernet - based on current proposed\_master branch
\item 1G Ethernet with redundancy support (see \ref{ssec:redundancy})
\item 10G Ethernet
\item 10G Ethernet with redundancy support (see \ref{ssec:redundancy})
\end{enumerate}
The firmware didn't have to be functional nor did it need to implement.
\section{Work done}
\subsection{Build system}
Project used to evaluate resource utilisation may be easily rebuild with HDLmake. It required small changes in syn/scb\_18ports/Manifest.py file.
\subsection{Block RAM}
Netlist representation of Block RAM was replaced by Xilinx Parametized Macro (XPM).
Netlists were removed because they are are not supported by Vivado.
\subsection{Xilinx primitives}
Input and output buffer primitives have been replaced by US+ family counterparts.
Some changes were also required in block platform/xilinx/oserdes\_8\_to\_1.vhd. Oserdes resolution has increased in US+.
\subsection{Gigabit transceivers}
Original Ethernet phys have been replaced with Xilinx IPcore "UltraScale FPGAs Transceivers Wizard". Separate versions were created for 1G Ethernet (line rate 1.25 Gb/s, 125 MHz clock, 20b internal data width \ref{fig:1g_conf}) and 10G Ethernet (line rate 12.5, 156.25 MHz clock, 40b internal data width \ref{fig:10g_conf}).
A generate loop (concatenate\_gen) was added to scb\_top\_synthesis to adjust existing phy interface to IPcore ports. Interconnect between the design and phys is unlikely to be functional, but should prevent Vivado from removing any major components.
\begin{figure}[h]
\caption{Gigabit transceivers configuration}
\label{fig:1g_conf}
\includegraphics[scale=0.5]{images/phy_1g.png}
\end{figure}
\begin{figure}[h]
\caption{10 Gigabit transceivers configuration}
\label{fig:10g_conf}
\includegraphics[scale=0.5]{images/phy_10g.png}
\end{figure}
\subsection{Redundancy support}
\label{ssec:redundancy}
Code required to implement link redundancy was developed by Maciej Lipiński. It is available in ohwr repository in branches ML-PTP-support-150317 and TRUandRTUandEndpointAndSWcoreAndTATSU.
Branch TRUandRTUandEndpointAndSWcoreAndTATSU was already merged with proposed master. Following generics had to be activated in scb\_top\_bare instantiation in order to evaluate resource utilisation of TRU and TATSU components: g\_with\_TRU, g\_with\_TATSU.
Branch ML-PTP-support-150317 required merging into proposed\_master. Regular merging proved to be difficult, due to multiple merge conflicts. Instead ML-PTP-support-150317 was rebased on proposed master. This way conflicts in consecutive commits could be resolved one by one.
A PSU (component that is added in this branch) may be enabled with generic g\_with\_PSU.
\subsection{10Gb link}
Migration to 10Gb link requires changing reference clock frequency and link data width. Frequency change doesn't effect resource utilisation. Timing is not even verified during synthesis.
Change of the data width requires changes in some parts of the design.
Most of components passes the data as is, so it is sufficient to change record declaration in vhdl packages.
Vectors t\_wrf\_source\_out.dat, t\_phyif\_output.tx\_data and t\_phyif\_input.rx\_data were resized from 16 to 64 bytes.
The endpoint on the other hand contains multiple comparisons and assignments that assume certain (16 bit) data width. Changing data width in this component would require rewriting multiple FSM's.
It was decided to instantiate 4 endpoints in parallel instead. Each of the multiplicated endpoints processes 16 bit of the 64 data word received from the phys. Other control signals (rx\_k, tx\_disparity etc) are connected to all 4 endpoints. Data output of the endpoints is concatenated back into 64 bit array. Other outputs of the endpoints are xored in order to make sure that nothing will be over optimised during synthesis. Vector t\_ep\_internal\_fabric.data has original 16 bit width.
The interface between original existing signals and multiplicated endpoint is located inside U\_Real\_Top/gen\_endpoints\_and\_phys generate loop.
\section{Found issues}
\subsection{Ext PLL} % (fold)
A minimal frequency of MMCM block was increased to ~14Mhz in US+ family. A U\_Ext\_PLL1 that generated 100 MHz clock from 10 MHz input will will not work correctly in US+ FPGA.
\subsection{Latch} % (fold)
A latch reported by Vivado was fixed in commit 16c02da485ed4aaea17b8c242b52b40d2cc2481c.
\section{Summary}
Figures \ref{fig:1g_nored_res}, \ref{fig:1g_red_res}, \ref{fig:10g_nored_res} and \ref{fig:10g_red_res} show resource utilisation estimated by Vivado IDE.
Resource utilisation with 10 Gb links barely reaches 50\% on LUT's and 45\% on BRAM.
\begin{figure}[h]
\caption{Resource utilisation with 1Gb serial links and without redundancy components.}
\label{fig:1g_nored_res}
\includegraphics[scale=0.75]{../resource_util_screenshots/1g_noredundancy.png}
\end{figure}
\begin{figure}[h]
\caption{Resource utilisation with 1Gb serial links and with redundancy components enabled.}
\label{fig:1g_red_res}
\includegraphics[scale=0.75]{../resource_util_screenshots/1g_redundancy_2.png}
\end{figure}
\begin{figure}[h]
\caption{Resource utilisation with 10Gb serial links and without redundancy components.}
\label{fig:10g_nored_res}
\includegraphics[scale=0.75]{../resource_util_screenshots/10g_noredundancy.png}
\end{figure}
\begin{figure}[h]
\caption{Resource utilisation with 10Gb serial links and with redundancy components enabled.}
\label{fig:10g_red_res}
\includegraphics[scale=0.75]{../resource_util_screenshots/10g_redundancy_2.png}
\end{figure}
\end{document}
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