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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit 7a165117 authored by Maciej Lipinski's avatar Maciej Lipinski
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make it implement

parent 575a30f6
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Showing with 21 additions and 18 deletions
general-cores @ 282fa737
Subproject commit 17d08e592c482848bf1ce9401f39a2a8749d04f4
Subproject commit 282fa73785a24d00a2f4207d6c67b8d366c13b02
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 7a165117
......@@ -452,23 +452,23 @@ begin -- rtl
slave_o => cnx_master_in(c_SLAVE_TIMER),
desc_o => open);
U_GEN_10_MHZ: xwrsw_gen_10mhz
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
rst_n_i => rst_sys_n_i,
clk_i => clk_sys_i,
pps_i => pps_csync,
pps_valid_i => pps_valid,
clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o,
clk_500_o => clk_500_o,
ppsdel_tap_i => ppsdel_tap_i,
ppsdel_tap_o => ppsdel_tap_o,
ppsdel_tap_wr_o => ppsdel_tap_wr_o,
slave_i => cnx_master_out(c_SLAVE_GEN10),
slave_o => cnx_master_in(c_SLAVE_GEN10));
-- U_GEN_10_MHZ: xwrsw_gen_10mhz
-- generic map (
-- g_interface_mode => PIPELINED,
-- g_address_granularity => BYTE)
-- port map (
-- rst_n_i => rst_sys_n_i,
-- clk_i => clk_sys_i,
-- pps_i => pps_csync,
-- pps_valid_i => pps_valid,
-- clk_aux_p_o => clk_aux_p_o,
-- clk_aux_n_o => clk_aux_n_o,
-- clk_500_o => clk_500_o,
-- ppsdel_tap_i => ppsdel_tap_i,
-- ppsdel_tap_o => ppsdel_tap_o,
-- ppsdel_tap_wr_o => ppsdel_tap_wr_o,
-- slave_i => cnx_master_out(c_SLAVE_GEN10),
-- slave_o => cnx_master_in(c_SLAVE_GEN10));
sel_clk_sys_o <= gpio_out(0);
pll_reset_n_o <= gpio_out(1);
......
top/scb_18ports/scb_top_synthesis.xdc
View file @ 7a165117
......@@ -148,6 +148,9 @@ set_property PACKAGE_PIN T8 [get_ports {gtx_clk_p_i[4]}]
# ML- added to overcome errors
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_25mhz_BUFG]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets U_CLKEXT_BUF/O]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_sys_startup]
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