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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit 7c50aa5e authored by Marek Gumiński's avatar Marek Gumiński
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[PSU] added signal from rt_subsystem to PSU to clear bit indicating announce msg reception

parent eef777b5
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modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 7c50aa5e
......@@ -132,6 +132,7 @@ entity wrsw_rt_subsystem is
selected_ref_clk_o : out std_logic_vector(g_num_rx_clocks-1 downto 0);
holdover_on_o : out std_logic;
rx_holdover_msg_i : in std_logic;
rx_holdover_clr_o : out std_logic;
-- Debug
spll_dbg_o : out std_logic_vector(5 downto 0)
);
......@@ -180,6 +181,7 @@ architecture rtl of wrsw_rt_subsystem is
selected_ref_clk_o : out std_logic_vector(g_num_ref_inputs-1 downto 0);
holdover_on_o : out std_logic;
rx_holdover_msg_i : in std_logic;
rx_holdover_clr_o : out std_logic;
int_o : out std_logic;
debug_o : out std_logic_vector(5 downto 0);
dbg_fifo_irq_o : out std_logic);
......@@ -371,6 +373,7 @@ begin -- rtl
selected_ref_clk_o => selected_ref_clk_o,
holdover_on_o => holdover_on_o,
rx_holdover_msg_i => rx_holdover_msg_i,
rx_holdover_clr_o => rx_holdover_clr_o ,
int_o => cpu_irq_vec(0),
debug_o => spll_dbg_o);
......
top/bare_top/scb_top_bare.vhd
View file @ 7c50aa5e
......@@ -464,6 +464,7 @@ architecture rtl of scb_top_bare is
signal rt_psu_sel_ref : std_logic_vector(g_num_ports-1 downto 0);
signal rt_psu_holdover : std_logic;
signal rt_psu_rx_holdover_msg: std_logic;
signal rt_psu_rx_holdover_clr: std_logic;
begin
......@@ -653,6 +654,7 @@ begin
selected_ref_clk_o => rt_psu_sel_ref,
holdover_on_o => rt_psu_holdover,
rx_holdover_msg_i => rt_psu_rx_holdover_msg,
rx_holdover_clr_o => rt_psu_rx_holdover_clr,
spll_dbg_o => spll_dbg_o);
ppsdel_tap_out <= ppsdel_tap_wide_out(8 downto 4);
......@@ -1120,6 +1122,7 @@ begin
selected_ref_clk_i => rt_psu_sel_ref,
holdover_on_i => rt_psu_holdover,
rx_holdover_msg_o => rt_psu_rx_holdover_msg,
rx_holdover_clr_i => rt_psu_rx_holdover_clr,
-- config via WB
wb_i => cnx_master_out(c_SLAVE_PSU),
......
top/bare_top/wrsw_components_pkg.vhd
View file @ 7c50aa5e
......@@ -253,6 +253,7 @@ package wrsw_components_pkg is
clk_rx_status_i : in std_logic_vector(g_num_rx_clocks-1 downto 0) :=(others=>'0');
selected_ref_clk_o : out std_logic_vector(g_num_ref_inputs-1 downto 0);
holdover_on_o : out std_logic;
rx_holdover_clr_o : out std_logic;
rx_holdover_msg_i : in std_logic);
end component;
......@@ -482,6 +483,7 @@ package wrsw_components_pkg is
selected_ref_clk_i : in std_logic_vector(g_port_number-1 downto 0);
holdover_on_i : in std_logic;
rx_holdover_msg_o : out std_logic;
rx_holdover_clr_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 7c50aa5e
......@@ -258,6 +258,7 @@ package wrsw_top_pkg is
selected_ref_clk_o : out std_logic_vector(g_num_rx_clocks-1 downto 0);
holdover_on_o : out std_logic;
rx_holdover_msg_i : in std_logic;
rx_holdover_clr_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0));
end component;
......@@ -549,6 +550,7 @@ package wrsw_top_pkg is
selected_ref_clk_i : in std_logic_vector(g_port_number-1 downto 0);
holdover_on_i : in std_logic;
rx_holdover_msg_o : out std_logic;
rx_holdover_clr_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
......
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