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Resource Evaluation of WR switch HDL for Ultrascale Plus
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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commits
80f1d321
Commit
80f1d321
authored
Aug 21, 2019
by
Marek Gumiński
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Replaced some vector ranges with constants (partially)
parent
42cccc9e
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scb_top_synthesis.vhd
top/scb_18ports/scb_top_synthesis.vhd
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top/scb_18ports/scb_top_synthesis.vhd
View file @
80f1d321
...
...
@@ -564,16 +564,16 @@ begin
phy_block
:
block
signal
to_phys_tx_data
:
STD_LOGIC_VECTOR
(
287
DOWNTO
0
);
signal
to_phys_tx_k
:
STD_LOGIC_VECTOR
(
143
DOWNTO
0
);
signal
to_phys_tx_data
:
STD_LOGIC_VECTOR
(
c_NUM_PHYS
*
16-1
DOWNTO
0
);
signal
to_phys_tx_k
:
STD_LOGIC_VECTOR
(
c_NUM_PHYS
*
8-1
DOWNTO
0
);
signal
to_phys_rst
:
STD_LOGIC
;
signal
from_phys_rx_data
:
STD_LOGIC_VECTOR
(
287
DOWNTO
0
);
signal
from_phys_rx_k
:
STD_LOGIC_VECTOR
(
287
DOWNTO
0
);
signal
from_phys_disp_err
:
STD_LOGIC_VECTOR
(
287
DOWNTO
0
);
signal
from_phys_rx_comma
:
STD_LOGIC_VECTOR
(
143
DOWNTO
0
);
signal
from_phys_enc_err
:
STD_LOGIC_VECTOR
(
143
DOWNTO
0
);
signal
from_phys_rx_data
:
STD_LOGIC_VECTOR
(
c_NUM_PHYS
*
16-1
DOWNTO
0
);
signal
from_phys_rx_k
:
STD_LOGIC_VECTOR
(
c_NUM_PHYS
*
16-1
DOWNTO
0
);
signal
from_phys_disp_err
:
STD_LOGIC_VECTOR
(
c_NUM_PHYS
*
16-1
DOWNTO
0
);
signal
from_phys_rx_comma
:
STD_LOGIC_VECTOR
(
c_NUM_PHYS
*
8-1
DOWNTO
0
);
signal
from_phys_enc_err
:
STD_LOGIC_VECTOR
(
c_NUM_PHYS
*
8-1
DOWNTO
0
);
signal
c25m_to_phys_rst
:
STD_LOGIC
;
signal
from_phys_tx_enc_err_common
:
STD_LOGIC
;
...
...
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