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Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit 87519995 authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Marek Gumiński
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[PSU] added communication between SoftPLL and PTP support unit

parent 87054652
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modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
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......@@ -129,6 +129,9 @@ entity wrsw_rt_subsystem is
-- used for switchover between them
clk_rx_status_i : in std_logic_vector(g_num_rx_clocks-1 downto 0) :=(others=>'0');
selected_ref_clk_o : out std_logic_vector(g_num_rx_clocks-1 downto 0);
holdover_on_o : out std_logic;
rx_holdover_msg_i : in std_logic;
-- Debug
spll_dbg_o : out std_logic_vector(5 downto 0)
);
......@@ -173,6 +176,10 @@ architecture rtl of wrsw_rt_subsystem is
out_status_o : out std_logic_vector(4*g_num_outputs-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
clk_rx_status_i : in std_logic_vector(g_num_ref_inputs-1 downto 0) :=(others=>'0');
selected_ref_clk_o : out std_logic_vector(g_num_ref_inputs-1 downto 0);
holdover_on_o : out std_logic;
rx_holdover_msg_i : in std_logic;
int_o : out std_logic;
debug_o : out std_logic_vector(5 downto 0);
dbg_fifo_irq_o : out std_logic);
......@@ -361,6 +368,9 @@ begin -- rtl
slave_i => cnx_master_out(c_SLAVE_SOFTPLL),
slave_o => cnx_master_in(c_SLAVE_SOFTPLL),
clk_rx_status_i => clk_rx_status_i,
selected_ref_clk_o => selected_ref_clk_o,
holdover_on_o => holdover_on_o,
rx_holdover_msg_i => rx_holdover_msg_i,
int_o => cpu_irq_vec(0),
debug_o => spll_dbg_o);
......
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