Disabled inter-clock timing analysis.

Just to try implementation....

Disabled inter-clock timing analysis.
Just to try implementation....
8a8f768f · Marek Gumiński · 227c0d4f · 8a8f768f
Commit 8a8f768f authored Aug 12, 2019 by Marek Gumiński
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scb_top_synthesis.xdc top/scb_18ports/scb_top_synthesis.xdc +120 -0

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--- a/top/scb_18ports/scb_top_synthesis.xdc
+++ b/top/scb_18ports/scb_top_synthesis.xdc