Skip to content

R
Resource Evaluation of WR switch HDL for Ultrascale Plus
Commit 95211a73 authored by Marek Gumiński's avatar Marek Gumiński
Browse files
Options

Update of documentation. 

Updated resource utilization screenshots.
Added short resource comparison of different versions.
parent 05838a8a
Hide whitespace changes
Inline Side-by-side
Showing with 146 additions and 14 deletions
doc/report/images/wrs.png
View replaced file @ 05838a8a View file @ 95211a73
doc/report/images/wrs.png

82.5 KB | W: | H:

doc/report/images/wrs.png

143 KB | W: | H:

doc/report/images/wrs.png
doc/report/images/wrs.png
doc/report/images/wrs.png
doc/report/images/wrs.png
  • 2-up
  • Swipe
  • Onion skin
doc/report/main.pdf
View file @ 95211a73
No preview for this file type
doc/report/main.tex
View file @ 95211a73
......@@ -2,6 +2,8 @@
\input{"cti_style_doc.tex"}
\usepackage{multirow}
\newcommand{\CtiDocumentTitle}{WRS resource utilisation }
\newcommand{\CtiHeader}{Evaluation of WRS firmware resource utilisation}
\newcommand{\CtiSubtitle}{on Xilinx US+ FPGA}
......@@ -27,7 +29,7 @@ Author={Creotech Instruments S.A.}}
\section{Introduction}
Presented report summarizes evaluation of White Rabbit Switch (WRS) firmware resource evaluation. Firmware is evaluated for Xilinx Zynq UltraScale+ (US+) MPSoC XCZU11EG-1FFVC1156E \ref{fig:fpga_over}.
Presented report summarizes evaluation of White Rabbit Switch (WRS) firmware resource evaluation. Firmware is evaluated for Xilinx Zynq UltraScale+ (US+) MPSoC XCZU11EG-1FFVC1156E (see figure \ref{fig:fpga_over}).
\begin{figure}[h]
......@@ -39,9 +41,9 @@ Author={Creotech Instruments S.A.}}
The firmware was supposed to be tested in following configurations:
\begin{enumerate}
\item 1G Ethernet - based on current proposed\_master branch
\item 1G Ethernet with redundancy support (see \ref{ssec:redundancy})
\item 1G Ethernet with redundancy support (see figure \ref{ssec:redundancy})
\item 10G Ethernet
\item 10G Ethernet with redundancy support (see \ref{ssec:redundancy})
\item 10G Ethernet with redundancy support (see figure \ref{ssec:redundancy})
\end{enumerate}
The firmware didn't have to be functional nor did it need to implement.
......@@ -62,7 +64,7 @@ Author={Creotech Instruments S.A.}}
Some changes were also required in block platform/xilinx/oserdes\_8\_to\_1.vhd. Oserdes resolution has increased in US+.
\subsection{Gigabit transceivers}
Original Ethernet phys have been replaced with Xilinx IPcore "UltraScale FPGAs Transceivers Wizard". Separate versions were created for 1G Ethernet (line rate 1.25 Gb/s, 125 MHz clock, 20b internal data width \ref{fig:1g_conf}) and 10G Ethernet (line rate 12.5, 156.25 MHz clock, 40b internal data width \ref{fig:10g_conf}).
Original Ethernet phys have been replaced with Xilinx IPcore "UltraScale FPGAs Transceivers Wizard". Separate versions were created for 1G Ethernet (line rate 1.25 Gb/s, 125 MHz clock, 20b internal data width as shown in figure \ref{fig:1g_conf}) and 10G Ethernet (line rate 12.5, 156.25 MHz clock, 40b internal data width as shown in figure \ref{fig:10g_conf}).
A generate loop (concatenate\_gen) was added to scb\_top\_synthesis to adjust existing phy interface to IPcore ports. Interconnect between the design and phys is unlikely to be functional, but should prevent Vivado from removing any major components.
......@@ -88,9 +90,10 @@ Author={Creotech Instruments S.A.}}
A PSU (component that is added in this branch) may be enabled with generic g\_with\_PSU.
\subsection{10Gb link}
\subsection{10 Gb link}
\label{ssec:10g}
Migration to 10Gb link requires changing reference clock frequency and link data width. Frequency change doesn't effect resource utilisation. Timing is not even verified during synthesis.
Migration to 10 Gb link requires changing reference clock frequency and link data width. Frequency change doesn't effect resource utilisation. Timing is not even verified during synthesis.
Change of the data width requires changes in some parts of the design.
......@@ -112,13 +115,137 @@ Author={Creotech Instruments S.A.}}
\subsection{Latch} % (fold)
A latch reported by Vivado was fixed in commit 16c02da485ed4aaea17b8c242b52b40d2cc2481c.
\section{Verification}
\subsection{1 Gb link}
The design was verified by comparing resource utilisation of original WRS firmware for Virtex 6 FPGA and US+ version.
The Virtex firmware was implemented with keep\_hierarchy property disabled, as it is in the repository, so the resource distribution between components may be distorted. US+ version is synthesised with keep\_hierarchy enabled.
Comparison of LUT and Register usage is simple, as both ISE and Vivado report them in a similar manner.
Comparison of BRAM usage is more complicated because ISE reports number of BRAM instantiations without diverting between 18 kB and 36 kB blocks. Vivado counts 18 kB blocks as 0.5 of a BRAM.
Comparison is given in table \ref{tab:orig}.
LUT utilisation of subcomponents (i.e U\_RTU, U\_Endpoint\_X) differ quite significantly, but total utilisation of U\_Real\_Top and top are very similar.
The differences in subcomponents are probably caused by flatten hierarchy.
Register utilisation matches almost perfectly.
BRAM utilisation seem do differ a lot, but it is caused by different way of reporting 18 kB BRAMs. Design summary shows that the whole design uses 165 RAMB36 and 121 RAMB18 (286 in total).
Vivado would report it as 165+0.5*121=225, so the difference is 9 BRAMs.
The resource utilisation of firmware with redundancy was compared with the original one.
As expected utilisation didn't change of any of subcomponents listed in table \ref{tab:orig} except for increase in top and U\_Real\_Top caused by addition of subcomponents U\_TRU, U\_PSU, U\_TATSU. Total utilisation of new subcomponents match the increase in top module usage.
\begin{table}
\centering
\caption{Extract of resource utilisation report of original firmware synthesized for Virtex 6 and US+ FPGA.}
\begin{tabular}{ll|lll}
\label{tab:orig}
& & \textbf{LUT}& \textbf{REG}& \textbf{BRAM} \\
\hline
\multirow{2}{*}{\textbf{top}} & Virtex 6 & 96k & 82k & 286 \\
& US+ & 108k & 91k & 216 \\
\hline
\multirow{2}{*}{\textbf{U\_Real\_Top}} & Virtex 6 & 92k & 80k & 286 \\
& US+ & 102k & 82k & 216 \\
\hline
\multirow{2}{*}{\textbf{U\_RT\_Subsystem}} & Virtex 6 & 2.4k & 5.7k & 34 \\
& US+ & 5.1k & 5.7k & 40.5 \\
\hline
\multirow{2}{*}{\textbf{U\_Swcore}} & Virtex 6 & 37.4k & 29.5k & 83 \\
& US+ & 44.8k & 30.6k & 55 \\
\hline
\multirow{2}{*}{\textbf{U\_RTU}} & Virtex 6 & 0.8k & 5.4k & 24 \\
& US+ & 6.4k & 5.4k & 23 \\
\hline
\multirow{2}{*}{\textbf{U\_Nic}} & Virtex 6 & 0.2k & 0.8k & 11 \\
& US+ & 0.8k & 0.8k & 10.5 \\
\hline
\multirow{2}{*}{\textbf{U\_Endpoint\_X}} & Virtex 6 & 0.2k & 1.7k & 6 \\
& US+ & 1.7k & 1.8k & 3.5
\end{tabular}
\end{table}
\begin{table}
\centering
\caption{Comparison between original version and one with redundancy support.}
\begin{tabular}{ll|lll}
\label{tab:red_nored}
& & \textbf{LUT}& \textbf{REG}& \textbf{BRAM} \\
\hline
\multirow{3}{*}{\textbf{top}} & Virtex 6 & 96k & 82k & 286 \\
& US+ & 108k & 91k & 216 \\
& US+ Redundancy & 114k & 94k & 240 \\
\hline
\multirow{3}{*}{\textbf{U\_Real\_Top}} & Virtex 6 & 92k & 80k & 286 \\
& US+ & 102k & 82k & 216 \\
& US+ Redundancy & 108k & 85k & 240 \\
\hline
\multirow{2}{*}{\textbf{U\_TRU}} & Virtex 6 & - & - & - \\
& US+ & - & - & - \\
& US+ Redundancy & 4.5k & 1.5k & 24 \\
\hline
\multirow{2}{*}{\textbf{U\_PSU}} & Virtex 6 & - & - & - \\
& US+ & - & - & - \\
& US+ Redundancy & 0.7k & 0.3k & 0.5 \\
\hline
\multirow{2}{*}{\textbf{U\_TATSU}} & Virtex 6 & - & - & - \\
& US+ & - & - & - \\
& US+ Redundancy & 0.5k & 0.3k & 0
\end{tabular}
\end{table}
\subsection{10 Gb link}
Table \ref{tab:10g} shows resource utilisatoin comparison of 1 Gb and 10 Gb versions of the original (no redundancy) firmware.
As described in section \ref{ssec:10g} 1 Gb endpoints were used in 10 Gb version of the firmware. The endpoints were multiplicated to simulate increased complexity. As shown in table \ref{tab:10g} resource utilisation of single endpoint didn't change, but total utilisation increased 4 times (there were 19 endpoints, now there is 4*19=76).
Little difference of resource utilisation is seen in U\_RTU, U\_RT\_Subsystem and U\_Nic.
The biggest difference is visible in U\_Swcore. BRAM utilisation changed mainly due to increase of "MULTIPORT\_MEMORY", that is used for buffering of data packets. LUT and register utilisation increased approximately 1.5 times.
Total increase of top and U\_Real\_Top roughly matches increased consumption of multiplicatated endpoints and changed U\_Swcore.
\begin{table}
\centering
\caption{Comparison of resource utilisation between 1 Gb and 10 Gb firmware without redundancy support.}
\begin{tabular}{ll|lll}
\label{tab:10g}
& & \textbf{LUT}& \textbf{REG}& \textbf{BRAM} \\
\hline
\multirow{2}{*}{\textbf{top}} & 1 Gb & 108k & 91k & 216 \\
& 10 Gb & 212k & 200k & 506 \\
\hline
\multirow{2}{*}{\textbf{U\_Real\_Top}} & 1 Gb & 102 & 82k & 216 \\
& 10 Gb & 212k & 200k & 506 \\
\hline
\multirow{2}{*}{\textbf{U\_RT\_Subsystem}} & 1 Gb & 5.1k & 5.7k & 40.5 \\
& 10 Gb & 5.1k & 5.7k & 40.5 \\
\hline
\multirow{2}{*}{\textbf{U\_Swcore}} & 1 Gb & 44.8k & 30.6k & 55 \\
& 10 Gb & 57.8k & 51.7k & 115.5 \\
\hline
\multirow{2}{*}{\textbf{U\_RTU}} & 1 Gb & 6.4k & 5.4k & 23 \\
& 10 Gb & 6.4k & 5.4k & 23 \\
\hline
\multirow{2}{*}{\textbf{U\_Nic}} & 1 Gb & 0.8k & 0.8k & 10.5 \\
& 10 Gb & 0.9k & 0.9k & 11.5 \\
\hline
\multirow{2}{*}{\textbf{U\_Endpoint\_X}} & 1 Gb & 1.7k & 1.8k & 3.5 \\
& 10 Gb & 1.7k & 1.8k & 3.5
\end{tabular}
\end{table}
\section{Summary}
Figures \ref{fig:1g_nored_res}, \ref{fig:1g_red_res}, \ref{fig:10g_nored_res} and \ref{fig:10g_red_res} show resource utilisation estimated by Vivado IDE.
Resource utilisation with 10 Gb links barely reaches 50\% on LUT's and 45\% on BRAM.
\begin{figure}[h]
\caption{Resource utilisation with 1Gb serial links and without redundancy components.}
\label{fig:1g_nored_res}
......
doc/report/title_page.tex
View file @ 95211a73
......@@ -4,10 +4,6 @@
\vskip 1 true in
% \begin{center}
% \textbf{{\Huge \CtiDocumentTitle}} \bigskip
% \end{center}
\begin{wrapfigure}{l}{0.01\textwidth}
\begin{center}
\vspace{-35pt}
......@@ -22,15 +18,24 @@
\textbf{ {\indent \indent \LARGE \mbox{\CtiSubtitle}}}\\
% \vskip 0.8 true in
\vspace{3cm}
\begin{figure}[htbp!]
\centering
\includegraphics[width=14.5cm,height=15cm,keepaspectratio]{\CtiDocumentLogo}\\
\includegraphics[width=\textwidth,keepaspectratio]{\CtiDocumentLogo}\\
\end{figure}
\begin{center}
\end{center}
\vspace{3cm}
Prepared by Marek Gumiński
marek.guminski@creotech.pl
\vspace{1cm}
Copyright CERN 2019 
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment