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White Rabbit Switch - Gateware
Commit 0049da0a authored by Harvey Leicester's avatar Harvey Leicester
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afcz: endpoint 0 to nic, others to switching core. added endpoint/phy reset output to rt subsystem

parent 7303468f
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Showing with 52 additions and 76 deletions
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 0049da0a
......@@ -109,7 +109,7 @@ entity wrsw_rt_subsystem is
sel_clk_sys_o : out std_logic; -- system clock selection: 0 = startup
-- clock, 1 = PLL clock
rts_ep_rst_n_o : out std_logic := '0'; --endpoint reset, active low
-- Wired to IODelay in the top module for precise 1-PPS out alignment
-- with clk_aux
......@@ -510,9 +510,6 @@ begin -- rtl
pll_reset_n_o <= gpio_out(1);
cpu_reset_n <= not gpio_out(2) and rst_sys_n_i;
rst_n_o <= gpio_out(3);
gpio_in(4) <= ljd_board_detected;
gpio_in(7 downto 5) <= ljd_osc_freq_i;
......@@ -523,12 +520,13 @@ begin -- rtl
aux_sda_o <= '0';
gpio_in(8) <= aux_scl_i;
gpio_in(9) <= aux_sda_i;
rts_ep_rst_n_o <= gpio_out(10);
dac_main_value_o <= dac_out_data;
dac_main_load_o <= dac_out_load;
dac_helper_value_o <= dac_dmtd_data;
dac_helper_load_o <= dac_dmtd_load;
dac_helper_load_o <= dac_dmtd_load;
------------------------------------------------------
-- WRS Low jitter daughterboard
......
top/afcz_wrs_8p/afcz_wrs_8p_top.vhd
View file @ 0049da0a
......@@ -115,10 +115,10 @@ entity afcz_wrs_8p_top is
mgtclk1_225_p_i : in std_logic;
mgtclk1_225_n_i : in std_logic;
mgt227_tx_p_o : out std_logic_vector(0 downto 0);
mgt227_tx_n_o : out std_logic_vector(0 downto 0);
mgt227_rx_p_i : in std_logic_vector(0 downto 0);
mgt227_rx_n_i : in std_logic_vector(0 downto 0)
mgt227_tx_p_o : out std_logic_vector(3 downto 0);
mgt227_tx_n_o : out std_logic_vector(3 downto 0);
mgt227_rx_p_i : in std_logic_vector(3 downto 0);
mgt227_rx_n_i : in std_logic_vector(3 downto 0)
--mgt225_tx_p_o : out std_logic_vector(3 downto 0);
--mgt225_tx_n_o : out std_logic_vector(3 downto 0);
......@@ -130,8 +130,8 @@ end afcz_wrs_8p_top;
architecture Behavioral of afcz_wrs_8p_top is
constant c_NUM_PHYS : integer := 1;
constant c_NUM_PORTS : integer := 1;
constant c_NUM_PHYS : integer := 4;
constant c_NUM_PORTS : integer := 4;
function f_bool2int(x : boolean) return integer is
begin
......@@ -331,6 +331,7 @@ architecture Behavioral of afcz_wrs_8p_top is
attribute mark_debug : string;
attribute mark_debug of host_master_in :signal is "true";
attribute mark_debug of host_master_out :signal is "true";
attribute mark_debug of sel_clk_sys : signal is "true";
signal gth_refclk : std_logic_vector(c_NUM_PHYS-1 downto 0);
signal gth_txoutclk : std_logic_vector(c_NUM_PHYS-1 downto 0);
......@@ -376,7 +377,7 @@ architecture Behavioral of afcz_wrs_8p_top is
signal aux_sda_out : std_logic;
--c_NUM_PORTS > c_num_sfp_ports...
constant c_num_sfp_ports : integer := 1;
constant c_num_sfp_ports : integer := 4;
signal sfp_scl_in : std_logic_vector(c_NUM_PORTS-1 downto 0);
signal sfp_scl_out : std_logic_vector(c_NUM_PORTS-1 downto 0);
......@@ -644,19 +645,6 @@ begin
end generate gen_terminate_unused_phys;
--BUFGMUX_inst : BUFGCTRL
-- port map (
-- IGNORE0 => '0',
-- IGNORE1 => '0',
-- CE0 => '1',
-- CE1 => '1',
-- O => clk_sys,
-- I0 => clk_startup_i,
-- I1 => clk_ref,
-- S1 => sel_clk_sys,
-- S0 => NOT sel_clk_sys);
BUFGMUX_inst : BUFGCTRL
port map (
IGNORE0 => '0',
......@@ -666,8 +654,9 @@ begin
O => clk_sys,
I0 => clk_startup_i,
I1 => clk_ref,
S1 => debug_gpo(1),
S0 => NOT debug_gpo(1));
S1 => sel_clk_sys,
S0 => NOT sel_clk_sys);
fmc_3v8_enable_o <= '1';
......@@ -747,14 +736,14 @@ begin
g_num_ports => c_NUM_PORTS,
g_simulation => g_simulation,
g_without_network => false,
g_with_TRU => false,
g_with_TATSU => false,
g_with_TRU => true,
g_with_TATSU => true,
g_with_HWIU => true,
g_with_PSTATS => false,
g_with_PSTATS => true,
g_with_muxed_CS => false,
g_with_watchdog => false,
g_with_rtu => false,
g_with_swc => false,
g_with_rtu => true,
g_with_swc => true,
g_with_si57x => true,
g_si57x_is_helper => true,
g_inj_per_EP => "00" & x"0000",
......@@ -863,10 +852,10 @@ begin
--mgt227_tx_n_o <= gth_txn(7 downto 4); --FMC2
--mgt227_tx_p_o <= gth_txp(7 downto 4);
mgt227_tx_n_o <= gth_txn(0 downto 0); --FMC2
mgt227_tx_p_o <= gth_txp(0 downto 0);
gth_rxn(0 downto 0) <= mgt227_rx_n_i; --FMC2
gth_rxp(0 downto 0) <= mgt227_rx_p_i;
mgt227_tx_n_o <= gth_txn; --FMC2
mgt227_tx_p_o <= gth_txp;
gth_rxn <= mgt227_rx_n_i; --FMC2
gth_rxp <= mgt227_rx_p_i;
--gth_rxn(3 downto 0) <= mgt225_rx_n_i; --FMC1
......
top/bare_top/scb_top_bare.vhd
View file @ 0049da0a
......@@ -89,8 +89,8 @@ entity scb_top_bare is
-- for re-phasing the 10 MHz input as well as clocking the
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic; -- going to CLK2 SMC on the front pannel, by
clk_aux_n_o : out std_logic; -- default it's 10MHz, but is configurable
......@@ -499,16 +499,7 @@ architecture rtl of scb_top_bare is
signal dbg_gpio_out : std_logic_vector(7 downto 0);
signal dbg_gpio_in : std_logic_vector(7 downto 0);
signal ep_sys_rst_n : std_logic;
attribute mark_debug : string;
attribute mark_debug of ep_sys_rst_n : signal is "true";
attribute mark_debug of dbg_gpio_out : signal is "true";
attribute mark_debug of endpoint_snk_in : signal is "true";
attribute mark_debug of endpoint_snk_out : signal is "true";
attribute mark_debug of endpoint_src_in : signal is "true";
attribute mark_debug of endpoint_src_out : signal is "true";
signal rts_ep_rst_n : std_logic;
begin
......@@ -659,6 +650,7 @@ begin
pps_ext_o => pps_o_predelay,
sel_clk_sys_o => sel_clk_sys,
rts_ep_rst_n_o => rts_ep_rst_n,
ppsdel_tap_i => ppsdel_tap_out,
ppsdel_tap_o => ppsdel_tap_in,
......@@ -738,7 +730,7 @@ begin
--snk_o => endpoint_snk_out(c_NUM_PORTS),
--src_i => endpoint_src_in(c_NUM_PORTS),
--src_o => endpoint_src_out(c_NUM_PORTS),
snk_i => endpoint_src_out(0), --connect directly to enpoint
snk_i => endpoint_src_out(0), --connect directly to endpoint
snk_o => endpoint_src_in(0),
src_i => endpoint_snk_out(0),
src_o => endpoint_snk_in(0),
......@@ -770,9 +762,7 @@ begin
slave_i(0) => cnx_master_out(c_SLAVE_ENDPOINTS),
slave_o(0) => cnx_master_in(c_SLAVE_ENDPOINTS),
master_i => cnx_endpoint_in,
master_o => cnx_endpoint_out);
ep_sys_rst_n <= rst_n_periph and dbg_gpio_out(3);
master_o => cnx_endpoint_out);
gen_endpoints_and_phys : for i in 0 to c_NUM_PORTS-1 generate
U_Endpoint_X : xwr_endpoint
......@@ -803,8 +793,7 @@ begin
clk_sys_i => clk_sys_i,
clk_dmtd_i => clk_dmtd_i,
--rst_sys_n_i => rst_n_periph,
rst_sys_n_i => ep_sys_rst_n,
rst_sys_n_i => rts_ep_rst_n,
rst_ref_n_i => rst_periph_ref_n,
rst_dmtd_n_i => rst_periph_dmtd_n,
rst_txclk_n_i => rst_periph_txclk_n(i),
......@@ -900,27 +889,27 @@ begin
end generate gen_endpoints_and_phys;
--GEN_TIMING: for I in 0 to c_NUM_PORTS generate
-- -- improve timing
-- U_WRF_RXREG_X: xwrf_reg
-- port map (
-- rst_n_i => rst_n_periph,
-- clk_i => clk_sys_i,
-- snk_i => endpoint_src_out(i),
-- snk_o => endpoint_src_in(i),
-- src_o => wrfreg_src_out(i),
-- src_i => wrfreg_src_in(i));
-- U_WRF_TXREG_X: xwrf_reg
-- port map(
-- rst_n_i => rst_n_periph,
-- clk_i => clk_sys_i,
-- snk_i => swc_src_out(i),
-- snk_o => swc_src_in(i),
-- src_o => endpoint_snk_in(i),
-- src_i => endpoint_snk_out(i));
--end generate;
--ep 0 to nic, 1->3 to swc
GEN_TIMING: for I in 1 to c_NUM_PORTS-1 generate
-- improve timing
U_WRF_RXREG_X: xwrf_reg
port map (
rst_n_i => rst_n_periph,
clk_i => clk_sys_i,
snk_i => endpoint_src_out(i),
snk_o => endpoint_src_in(i),
src_o => wrfreg_src_out(i),
src_i => wrfreg_src_in(i));
U_WRF_TXREG_X: xwrf_reg
port map(
rst_n_i => rst_n_periph,
clk_i => clk_sys_i,
snk_i => swc_src_out(i),
snk_o => swc_src_in(i),
src_o => endpoint_snk_in(i),
src_i => endpoint_snk_out(i));
end generate;
gen_terminate_unused_eps: for i in c_NUM_PORTS to c_MAX_PORTS-1 generate
cnx_endpoint_in(i).ack <= '1';
......
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