swcore[v2->v3 port]: added Tom's pWB<->WRF adapters into the wrapper, so we have…

swcore[v2->v3 port]: added Tom's pWB<->WRF adapters into the wrapper, so we have a swcore which has pWB I/F, next step: change the simulation to test how it works

swcore[v2->v3 port]: added Tom's pWB<->WRF adapters into the wrapper, so we have…
swcore[v2->v3 port]: added Tom's pWB<->WRF adapters into the wrapper, so we have a swcore which has pWB I/F, next step: change the simulation to test how it works
043a60ca · Maciej Lipinski · 5e4a2c84 · 043a60ca · 043a60ca · 043a60ca
Commit 043a60ca authored Jan 17, 2012 by Maciej Lipinski
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Showing with 113 additions and 105 deletions

Manifest.py modules/wrsw_swcore/Manifest.py +2 -5

xswc_core.vhd modules/wrsw_swcore/xswc_core.vhd +110 -100

Manifest.py testbench/swcore/Manifest.py +1 -0

No files found.
--- a/modules/wrsw_swcore/Manifest.py
+++ b/modules/wrsw_swcore/Manifest.py
@@ -6,6 +6,7 @@
 #         "swc_pipelined_mux.vhd",
 #         "swc_async_multiport_mem.vhd"]

+
 files = [
 "swc_swcore_pkg.vhd",
 "swc_block_alloc.vhd",
@@ -27,9 +28,5 @@ files = [
 "swc_pck_transfer_output.vhd",
 "swc_prio_encoder.vhd",
 "swc_rr_arbiter.vhd",
-"generic_ssram_dualport_singleclock.vhd",
-#"wr_fec_pkg.vhd",
-#"wr_wb_to_wrf.vhd",
-#"xswc_core.vhd"
-#"../../ip_cores/general-cores"
+"xswc_core.vhd",
 ]
\ No newline at end of file
--- a/modules/wrsw_swcore/xswc_core.vhd
+++ b/modules/wrsw_swcore/xswc_core.vhd
--- a/testbench/swcore/Manifest.py
+++ b/testbench/swcore/Manifest.py
@@ -9,6 +9,7 @@ vlog_opt="+incdir+../../../sim "

 modules = {"local":
 		[ 
+		  "../../ip_cores/wr-cores",
 		  "../../ip_cores/general-cores/modules/genrams/",
 		  "../../modules/wrsw_swcore",
 		],