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Commit 085a9135 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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HDL: platform: altera module cleanup

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Makefile
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SRCS_VHDL = platform_specific.vhd \
alt_clock_divider.vhd \
generic_async_fifo_2stage.vhd \
generic_clock_mux3.vhd \
generic_pipelined_multiplier.vhd \
generic_ssram_dualport.vhd \
generic_sync_fifo.vhd \
generic_ssram_dualport_singleclock.vhd \
generic_ssram_dp_rw_rw.vhd
../genrams/genram_pkg.vhd \
../genrams/altera/generic_dpram.vhd \
../genrams/altera/generic_spram.vhd \
../genrams/altera/generic_sync_fifo.vhd \
../genrams/altera/generic_async_fifo.vhd \
../generic_ssram_dualport_singleclock.vhd
VPATH=../genrams/altera ../genrams
WORK = work
......
clock_divider.vhd deleted 100644 → 0
View file @ c2abae67
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: clock_divider.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 132 02/25/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY alt_clock_divider IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END alt_clock_divider;
ARCHITECTURE SYN OF alt_clock_divider IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
locked <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 8000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=clock_divider",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c1"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "62.500000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "clock_divider.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clock_divider_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
generic_async_fifo_2stage.vhd deleted 100644 → 0
View file @ c2abae67
-------------------------------------------------------------------------------
-- Title : Generic platform-independent asychronous (2-stage) FIFO
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : generic_async_fifo_2stage.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-16
-- Last update: 2010-12-07
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Async FIFO design for Altera
-------------------------------------------------------------------------------
-- Copyright (c) 2009
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2009-06-16 1.0 slayer Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity generic_async_fifo_2stage is
generic (
g_width : natural := 8;
g_depth : natural := 32;
g_almostfull_bit_threshold : natural := 3;
g_show_ahead : boolean := false;
g_with_usedw_ports : boolean := false
);
port
(
clear_i : in std_logic := '0';
d_i : in std_logic_vector (g_width-1 downto 0);
rd_clk_i : in std_logic;
rd_req_i : in std_logic;
wr_clk_i : in std_logic;
wr_req_i : in std_logic;
q_o : out std_logic_vector (g_width-1 downto 0);
rd_empty_o : out std_logic;
wr_full_o : out std_logic;
almost_full_o : out std_logic;
wr_usedw_o : out std_logic_vector(31 downto 0);
rd_usedw_o : out std_logic_vector(31 downto 0)
);
end generic_async_fifo_2stage;
architecture SYN of generic_async_fifo_2stage is
function log2 (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 32 bits
if (2**I > A) then
return(I-1);
end if;
end loop;
return(63);
end function log2;
constant c_mask_value : std_logic_vector(g_almostfull_bit_threshold -1 downto 0) := (others => '1');
signal sub_wire0 : std_logic;
signal sub_wire1 : std_logic;
signal sub_wire2 : std_logic_vector (g_width-1 downto 0);
signal words_used : std_logic_vector(log2(g_depth)-1 downto 0);
component dcfifo
generic (
intended_device_family : string;
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
rdsync_delaypipe : natural;
underflow_checking : string;
use_eab : string;
write_aclr_synch : string;
wrsync_delaypipe : natural
);
port (
wrclk : in std_logic;
rdempty : out std_logic;
rdreq : in std_logic;
aclr : in std_logic;
wrfull : out std_logic;
rdclk : in std_logic;
q : out std_logic_vector (g_width-1 downto 0);
wrreq : in std_logic;
data : in std_logic_vector (g_width-1 downto 0);
wrusedw : out std_logic_vector (log2(g_depth)-1 downto 0);
rdusedw : out std_logic_vector (log2(g_depth)-1 downto 0)
);
end component;
begin
rd_empty_o <= sub_wire0;
wr_full_o <= sub_wire1;
q_o <= sub_wire2(g_width-1 downto 0);
gen_with_showahead : if(g_show_ahead = true) generate
dcfifo_component : dcfifo -- 3stage
generic map (
intended_device_family => "Cyclone III",
lpm_numwords => g_depth,
lpm_showahead => "ON",
lpm_type => "dcfifo",
lpm_width => g_width,
lpm_widthu => log2(g_depth),
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 5
)
port map (
wrclk => wr_clk_i,
rdreq => rd_req_i,
aclr => clear_i,
rdclk => rd_clk_i,
wrreq => wr_req_i,
data => d_i,
rdempty => sub_wire0,
wrfull => sub_wire1,
q => sub_wire2,
wrusedw => words_used,
rdusedw => rd_usedw_o(log2(g_depth)-1 downto 0)
);
end generate gen_with_showahead;
gen_no_showahead : if(g_show_ahead = false) generate
dcfifo_component : dcfifo -- 3stage
generic map (
intended_device_family => "Cyclone III",
lpm_numwords => g_depth,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => g_width,
lpm_widthu => log2(g_depth),
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 5
)
port map (
wrclk => wr_clk_i,
rdreq => rd_req_i,
aclr => clear_i,
rdclk => rd_clk_i,
wrreq => wr_req_i,
data => d_i,
rdempty => sub_wire0,
wrfull => sub_wire1,
q => sub_wire2,
wrusedw => words_used,
rdusedw => rd_usedw_o(log2(g_depth)-1 downto 0)
);
end generate gen_no_showahead;
almost_full_check : process (wr_clk_i, clear_i)
begin -- process almost_full_check
if clear_i = '1' then -- asynchronous reset (active low)
almost_full_o <= '0';
elsif wr_clk_i'event and wr_clk_i = '1' then -- rising clock edge
if words_used(words_used'high downto words_used'high - g_almostfull_bit_threshold + 1) = c_mask_value then
almost_full_o <= '1';
else
almost_full_o <= '0';
end if;
end if;
end process almost_full_check;
wr_usedw_o(log2(g_depth)-1 downto 0) <= words_used;
wr_usedw_o(wr_usedw_o'high downto log2(g_depth)) <= (others => '0');
rd_usedw_o(rd_usedw_o'high downto log2(g_depth)) <= (others => '0');
end SYN;
generic_ssram_dp_rw_rw.vhd deleted 100644 → 0
View file @ c2abae67
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.platform_specific.all;
entity generic_ssram_dp_rw_rw is
generic(
g_width : integer;
g_addr_bits : integer;
g_size : integer;
g_init_file : string);
port(
clk_i : in std_logic;
wr_en_a_i : in std_logic;
addr_a_i : in std_logic_vector(g_addr_bits-1 downto 0);
data_a_i : in std_logic_vector(g_width-1 downto 0);
q_a_o : out std_logic_vector(g_width-1 downto 0);
wr_en_b_i : in std_logic;
addr_b_i : in std_logic_vector(g_addr_bits-1 downto 0);
data_b_i : in std_logic_vector(g_width-1 downto 0);
q_b_o : out std_logic_vector(g_width-1 downto 0));
end generic_ssram_dp_rw_rw;
architecture behavioral of generic_ssram_dp_rw_rw is
type t_ram_array is array(2**g_addr_bits-1 downto 0) of std_logic_vector(g_width-1 downto 0);
impure function f_load_from_file (file_name : in string) return t_ram_array is
file rfile : text is in file_name;
variable l : line;
variable ram : t_ram_array;
variable tmp : bit_vector(g_width-1 downto 0);
variable i : integer;
begin
if(file_name = "") then
return ram;
end if;
i := 0;
while (i<9999) loop
if endfile(rfile) then
return ram;
end if;
readline (rfile, l);
read (l, tmp);
if(i<2**g_addr_bits) then
ram(i) := to_stdLogicVector(tmp);
end if;
i :=i+1;
end loop;
return ram;
end function;
shared variable ram_array : t_ram_array := f_load_from_file(g_init_file);
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if(wr_en_a_i = '1') then
ram_array(conv_integer(addr_a_i)) := data_a_i;
end if;
q_a_o <= ram_array(conv_integer(addr_a_i));
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if(wr_en_b_i = '1') then
ram_array(conv_integer(addr_b_i)) := data_b_i;
end if;
q_b_o <= ram_array(conv_integer(addr_b_i));
end if;
end process;
end behavioral;
generic_ssram_dualport.vhd deleted 100644 → 0
View file @ c2abae67
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity generic_ssram_dualport is
generic (
g_width : natural := 8;
g_addr_bits : natural := 10;
g_size : natural := 1024);
port
(
data_i : in std_logic_vector (g_width-1 downto 0);
rd_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
rd_clk_i : in std_logic;
wr_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
wr_clk_i : in std_logic;
wr_en_i : in std_logic := '1';
q_o : out std_logic_vector (g_width-1 downto 0)
);
end generic_ssram_dualport;
architecture SYN of generic_ssram_dualport is
signal sub_wire0 : std_logic_vector (g_width-1 downto 0);
component altsyncram
generic (
address_aclr_b : string;
address_reg_b : string;
clock_enable_input_a : string;
clock_enable_input_b : string;
clock_enable_output_b : string;
intended_device_family : string;
lpm_type : string;
numwords_a : natural;
numwords_b : natural;
operation_mode : string;
outdata_aclr_b : string;
outdata_reg_b : string;
power_up_uninitialized : string;
widthad_a : natural;
widthad_b : natural;
width_a : natural;
width_b : natural;
width_byteena_a : natural
);
port (
wren_a : in std_logic;
clock0 : in std_logic;
clock1 : in std_logic;
address_a : in std_logic_vector (g_addr_bits-1 downto 0);
address_b : in std_logic_vector (g_addr_bits-1 downto 0);
q_b : out std_logic_vector (g_width-1 downto 0);
data_a : in std_logic_vector (g_width-1 downto 0)
);
end component;
begin
q_o <= sub_wire0(g_width-1 downto 0);
altsyncram_component : altsyncram
generic map (
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => g_size,
numwords_b => g_size,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
widthad_a => g_addr_bits,
widthad_b => g_addr_bits,
width_a => g_width,
width_b => g_width,
width_byteena_a => 1
)
port map (
wren_a => wr_en_i,
clock0 => wr_clk_i,
clock1 => rd_clk_i,
address_a => wr_addr_i,
address_b => rd_addr_i,
data_a => data_i,
q_b => sub_wire0
);
end SYN;
generic_sync_fifo.vhd deleted 100644 → 0
View file @ c2abae67
-------------------------------------------------------------------------------
-- Title : Generic platform-independent sychronous FIFO
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : generic_sync_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-16
-- Last update: 2010-06-11
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Sync FIFO design for Altera FPGAs
-------------------------------------------------------------------------------
-- Copyright (c) 2009
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2009-06-16 1.0 slayer Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity generic_sync_fifo is
generic (
g_width : natural := 8;
g_depth : natural := 32;
g_depth_log2 : natural := 5
);
port
(
clk_i : in std_logic;
clear_i : in std_logic := '0';
wr_req_i : in std_logic;
d_i : in std_logic_vector (g_width-1 downto 0);
rd_req_i : in std_logic;
q_o : out std_logic_vector (g_width-1 downto 0);
empty_o : out std_logic;
full_o : out std_logic;
usedw_o : out std_logic_vector(g_depth_log2-1 downto 0)
);
end generic_sync_fifo;
architecture SYN of generic_sync_fifo is
component scfifo
generic (
add_ram_output_register : string;
intended_device_family : string;
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
underflow_checking : string;
use_eab : string
);
port (
usedw : out std_logic_vector (g_depth_log2-1 downto 0);
rdreq : in std_logic;
sclr : in std_logic;
empty : out std_logic;
clock : in std_logic;
q : out std_logic_vector (g_width-1 downto 0);
wrreq : in std_logic;
data : in std_logic_vector (g_width-1 downto 0);
full : out std_logic
);
end component;
begin
scfifo_component : scfifo
generic map (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone III",
lpm_numwords => g_depth,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => g_width,
lpm_widthu => g_depth_log2,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON")
port map (
rdreq => rd_req_i,
sclr => clear_i,
clock => clk_i,
wrreq => wr_req_i,
data => d_i,
usedw => usedw_o,
empty => empty_o,
q => q_o,
full => full_o);
end SYN;
platform_specific.vhd
View file @ 085a9135
......@@ -9,79 +9,6 @@ use lpm.all;
package platform_specific is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component generic_async_fifo_2stage
generic (
g_width : natural;
g_depth : natural;
g_almostfull_bit_threshold : natural;
g_show_ahead : boolean := false;
g_with_usedw_ports : boolean := false);
port (
clear_i : in std_logic := '0';
d_i : in std_logic_vector (g_width-1 downto 0);
rd_clk_i : in std_logic;
rd_req_i : in std_logic;
wr_clk_i : in std_logic;
wr_req_i : in std_logic;
q_o : out std_logic_vector (g_width-1 downto 0);
rd_empty_o : out std_logic;
wr_full_o : out std_logic;
almost_full_o : out std_logic;
wr_usedw_o : out std_logic_vector(31 downto 0);
rd_usedw_o : out std_logic_vector(31 downto 0));
end component;
component generic_sync_fifo
generic (
g_width : natural;
g_depth : natural;
g_depth_log2 : natural);
port (
clk_i : in std_logic;
clear_i : in std_logic := '0';
wr_req_i : in std_logic;
d_i : in std_logic_vector (g_width-1 downto 0);
rd_req_i : in std_logic;
q_o : out std_logic_vector (g_width-1 downto 0);
empty_o : out std_logic;
full_o : out std_logic;
usedw_o : out std_logic_vector(g_depth_log2-1 downto 0));
end component;
component generic_ssram_dualport
generic (
g_width : natural;
g_addr_bits : natural;
g_size : natural);
port (
data_i : in std_logic_vector (g_width-1 downto 0);
rd_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
rd_clk_i : in std_logic;
wr_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
wr_clk_i : in std_logic;
wr_en_i : in std_logic := '1';
q_o : out std_logic_vector (g_width-1 downto 0));
end component;
component generic_ssram_dualport_singleclock
generic (
g_width : natural;
g_addr_bits : natural;
g_size : natural;
g_init_file : string := "UNUSED");
port (
data_i : in std_logic_vector (g_width-1 downto 0);
clk_i : in std_logic;
rd_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
wr_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
wr_en_i : in std_logic := '1';
q_o : out std_logic_vector (g_width-1 downto 0));
end component;
component alt_clock_divider
port (
inclk0 : in std_logic := '0';
......@@ -105,15 +32,6 @@ package platform_specific is
q_o : out std_logic_vector(g_width_out-1 downto 0));
end component;
component generic_clock_mux3
port (
clk_sel_i : in std_logic_vector(1 downto 0);
inclk0_i : in std_logic;
inclk1_i : in std_logic;
inclk2_i : in std_logic;
outclk_o : out std_logic);
end component;
end platform_specific;
-------------------------------------------------------------------------------
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