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Commit 085a9135 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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HDL: platform: altera module cleanup

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Makefile
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SRCS_VHDL = platform_specific.vhd \
alt_clock_divider.vhd \
generic_async_fifo_2stage.vhd \
generic_clock_mux3.vhd \
generic_pipelined_multiplier.vhd \
generic_ssram_dualport.vhd \
generic_sync_fifo.vhd \
generic_ssram_dualport_singleclock.vhd \
generic_ssram_dp_rw_rw.vhd
../genrams/genram_pkg.vhd \
../genrams/altera/generic_dpram.vhd \
../genrams/altera/generic_spram.vhd \
../genrams/altera/generic_sync_fifo.vhd \
../genrams/altera/generic_async_fifo.vhd \
../generic_ssram_dualport_singleclock.vhd
VPATH=../genrams/altera ../genrams
WORK = work
......
clock_divider.vhd deleted 100644 → 0
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generic_async_fifo_2stage.vhd deleted 100644 → 0
View file @ c2abae67
-------------------------------------------------------------------------------
-- Title : Generic platform-independent asychronous (2-stage) FIFO
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : generic_async_fifo_2stage.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-16
-- Last update: 2010-12-07
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Async FIFO design for Altera
-------------------------------------------------------------------------------
-- Copyright (c) 2009
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2009-06-16 1.0 slayer Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity generic_async_fifo_2stage is
generic (
g_width : natural := 8;
g_depth : natural := 32;
g_almostfull_bit_threshold : natural := 3;
g_show_ahead : boolean := false;
g_with_usedw_ports : boolean := false
);
port
(
clear_i : in std_logic := '0';
d_i : in std_logic_vector (g_width-1 downto 0);
rd_clk_i : in std_logic;
rd_req_i : in std_logic;
wr_clk_i : in std_logic;
wr_req_i : in std_logic;
q_o : out std_logic_vector (g_width-1 downto 0);
rd_empty_o : out std_logic;
wr_full_o : out std_logic;
almost_full_o : out std_logic;
wr_usedw_o : out std_logic_vector(31 downto 0);
rd_usedw_o : out std_logic_vector(31 downto 0)
);
end generic_async_fifo_2stage;
architecture SYN of generic_async_fifo_2stage is
function log2 (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 32 bits
if (2**I > A) then
return(I-1);
end if;
end loop;
return(63);
end function log2;
constant c_mask_value : std_logic_vector(g_almostfull_bit_threshold -1 downto 0) := (others => '1');
signal sub_wire0 : std_logic;
signal sub_wire1 : std_logic;
signal sub_wire2 : std_logic_vector (g_width-1 downto 0);
signal words_used : std_logic_vector(log2(g_depth)-1 downto 0);
component dcfifo
generic (
intended_device_family : string;
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
rdsync_delaypipe : natural;
underflow_checking : string;
use_eab : string;
write_aclr_synch : string;
wrsync_delaypipe : natural
);
port (
wrclk : in std_logic;
rdempty : out std_logic;
rdreq : in std_logic;
aclr : in std_logic;
wrfull : out std_logic;
rdclk : in std_logic;
q : out std_logic_vector (g_width-1 downto 0);
wrreq : in std_logic;
data : in std_logic_vector (g_width-1 downto 0);
wrusedw : out std_logic_vector (log2(g_depth)-1 downto 0);
rdusedw : out std_logic_vector (log2(g_depth)-1 downto 0)
);
end component;
begin
rd_empty_o <= sub_wire0;
wr_full_o <= sub_wire1;
q_o <= sub_wire2(g_width-1 downto 0);
gen_with_showahead : if(g_show_ahead = true) generate
dcfifo_component : dcfifo -- 3stage
generic map (
intended_device_family => "Cyclone III",
lpm_numwords => g_depth,
lpm_showahead => "ON",
lpm_type => "dcfifo",
lpm_width => g_width,
lpm_widthu => log2(g_depth),
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 5
)
port map (
wrclk => wr_clk_i,
rdreq => rd_req_i,
aclr => clear_i,
rdclk => rd_clk_i,
wrreq => wr_req_i,
data => d_i,
rdempty => sub_wire0,
wrfull => sub_wire1,
q => sub_wire2,
wrusedw => words_used,
rdusedw => rd_usedw_o(log2(g_depth)-1 downto 0)
);
end generate gen_with_showahead;
gen_no_showahead : if(g_show_ahead = false) generate
dcfifo_component : dcfifo -- 3stage
generic map (
intended_device_family => "Cyclone III",
lpm_numwords => g_depth,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => g_width,
lpm_widthu => log2(g_depth),
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 5
)
port map (
wrclk => wr_clk_i,
rdreq => rd_req_i,
aclr => clear_i,
rdclk => rd_clk_i,
wrreq => wr_req_i,
data => d_i,
rdempty => sub_wire0,
wrfull => sub_wire1,
q => sub_wire2,
wrusedw => words_used,
rdusedw => rd_usedw_o(log2(g_depth)-1 downto 0)
);
end generate gen_no_showahead;
almost_full_check : process (wr_clk_i, clear_i)
begin -- process almost_full_check
if clear_i = '1' then -- asynchronous reset (active low)
almost_full_o <= '0';
elsif wr_clk_i'event and wr_clk_i = '1' then -- rising clock edge
if words_used(words_used'high downto words_used'high - g_almostfull_bit_threshold + 1) = c_mask_value then
almost_full_o <= '1';
else
almost_full_o <= '0';
end if;
end if;
end process almost_full_check;
wr_usedw_o(log2(g_depth)-1 downto 0) <= words_used;
wr_usedw_o(wr_usedw_o'high downto log2(g_depth)) <= (others => '0');
rd_usedw_o(rd_usedw_o'high downto log2(g_depth)) <= (others => '0');
end SYN;
generic_ssram_dp_rw_rw.vhd deleted 100644 → 0
View file @ c2abae67
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
use work.platform_specific.all;
entity generic_ssram_dp_rw_rw is
generic(
g_width : integer;
g_addr_bits : integer;
g_size : integer;
g_init_file : string);
port(
clk_i : in std_logic;
wr_en_a_i : in std_logic;
addr_a_i : in std_logic_vector(g_addr_bits-1 downto 0);
data_a_i : in std_logic_vector(g_width-1 downto 0);
q_a_o : out std_logic_vector(g_width-1 downto 0);
wr_en_b_i : in std_logic;
addr_b_i : in std_logic_vector(g_addr_bits-1 downto 0);
data_b_i : in std_logic_vector(g_width-1 downto 0);
q_b_o : out std_logic_vector(g_width-1 downto 0));
end generic_ssram_dp_rw_rw;
architecture behavioral of generic_ssram_dp_rw_rw is
type t_ram_array is array(2**g_addr_bits-1 downto 0) of std_logic_vector(g_width-1 downto 0);
impure function f_load_from_file (file_name : in string) return t_ram_array is
file rfile : text is in file_name;
variable l : line;
variable ram : t_ram_array;
variable tmp : bit_vector(g_width-1 downto 0);
variable i : integer;
begin
if(file_name = "") then
return ram;
end if;
i := 0;
while (i<9999) loop
if endfile(rfile) then
return ram;
end if;
readline (rfile, l);
read (l, tmp);
if(i<2**g_addr_bits) then
ram(i) := to_stdLogicVector(tmp);
end if;
i :=i+1;
end loop;
return ram;
end function;
shared variable ram_array : t_ram_array := f_load_from_file(g_init_file);
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if(wr_en_a_i = '1') then
ram_array(conv_integer(addr_a_i)) := data_a_i;
end if;
q_a_o <= ram_array(conv_integer(addr_a_i));
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if(wr_en_b_i = '1') then
ram_array(conv_integer(addr_b_i)) := data_b_i;
end if;
q_b_o <= ram_array(conv_integer(addr_b_i));
end if;
end process;
end behavioral;
generic_ssram_dualport.vhd deleted 100644 → 0
View file @ c2abae67
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity generic_ssram_dualport is
generic (
g_width : natural := 8;
g_addr_bits : natural := 10;
g_size : natural := 1024);
port
(
data_i : in std_logic_vector (g_width-1 downto 0);
rd_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
rd_clk_i : in std_logic;
wr_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
wr_clk_i : in std_logic;
wr_en_i : in std_logic := '1';
q_o : out std_logic_vector (g_width-1 downto 0)
);
end generic_ssram_dualport;
architecture SYN of generic_ssram_dualport is
signal sub_wire0 : std_logic_vector (g_width-1 downto 0);
component altsyncram
generic (
address_aclr_b : string;
address_reg_b : string;
clock_enable_input_a : string;
clock_enable_input_b : string;
clock_enable_output_b : string;
intended_device_family : string;
lpm_type : string;
numwords_a : natural;
numwords_b : natural;
operation_mode : string;
outdata_aclr_b : string;
outdata_reg_b : string;
power_up_uninitialized : string;
widthad_a : natural;
widthad_b : natural;
width_a : natural;
width_b : natural;
width_byteena_a : natural
);
port (
wren_a : in std_logic;
clock0 : in std_logic;
clock1 : in std_logic;
address_a : in std_logic_vector (g_addr_bits-1 downto 0);
address_b : in std_logic_vector (g_addr_bits-1 downto 0);
q_b : out std_logic_vector (g_width-1 downto 0);
data_a : in std_logic_vector (g_width-1 downto 0)
);
end component;
begin
q_o <= sub_wire0(g_width-1 downto 0);
altsyncram_component : altsyncram
generic map (
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => g_size,
numwords_b => g_size,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
widthad_a => g_addr_bits,
widthad_b => g_addr_bits,
width_a => g_width,
width_b => g_width,
width_byteena_a => 1
)
port map (
wren_a => wr_en_i,
clock0 => wr_clk_i,
clock1 => rd_clk_i,
address_a => wr_addr_i,
address_b => rd_addr_i,
data_a => data_i,
q_b => sub_wire0
);
end SYN;
generic_sync_fifo.vhd deleted 100644 → 0
View file @ c2abae67
-------------------------------------------------------------------------------
-- Title : Generic platform-independent sychronous FIFO
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : generic_sync_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-16
-- Last update: 2010-06-11
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Sync FIFO design for Altera FPGAs
-------------------------------------------------------------------------------
-- Copyright (c) 2009
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2009-06-16 1.0 slayer Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity generic_sync_fifo is
generic (
g_width : natural := 8;
g_depth : natural := 32;
g_depth_log2 : natural := 5
);
port
(
clk_i : in std_logic;
clear_i : in std_logic := '0';
wr_req_i : in std_logic;
d_i : in std_logic_vector (g_width-1 downto 0);
rd_req_i : in std_logic;
q_o : out std_logic_vector (g_width-1 downto 0);
empty_o : out std_logic;
full_o : out std_logic;
usedw_o : out std_logic_vector(g_depth_log2-1 downto 0)
);
end generic_sync_fifo;
architecture SYN of generic_sync_fifo is
component scfifo
generic (
add_ram_output_register : string;
intended_device_family : string;
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
underflow_checking : string;
use_eab : string
);
port (
usedw : out std_logic_vector (g_depth_log2-1 downto 0);
rdreq : in std_logic;
sclr : in std_logic;
empty : out std_logic;
clock : in std_logic;
q : out std_logic_vector (g_width-1 downto 0);
wrreq : in std_logic;
data : in std_logic_vector (g_width-1 downto 0);
full : out std_logic
);
end component;
begin
scfifo_component : scfifo
generic map (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone III",
lpm_numwords => g_depth,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => g_width,
lpm_widthu => g_depth_log2,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON")
port map (
rdreq => rd_req_i,
sclr => clear_i,
clock => clk_i,
wrreq => wr_req_i,
data => d_i,
usedw => usedw_o,
empty => empty_o,
q => q_o,
full => full_o);
end SYN;
platform_specific.vhd
View file @ 085a9135
......@@ -9,79 +9,6 @@ use lpm.all;
package platform_specific is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component generic_async_fifo_2stage
generic (
g_width : natural;
g_depth : natural;
g_almostfull_bit_threshold : natural;
g_show_ahead : boolean := false;
g_with_usedw_ports : boolean := false);
port (
clear_i : in std_logic := '0';
d_i : in std_logic_vector (g_width-1 downto 0);
rd_clk_i : in std_logic;
rd_req_i : in std_logic;
wr_clk_i : in std_logic;
wr_req_i : in std_logic;
q_o : out std_logic_vector (g_width-1 downto 0);
rd_empty_o : out std_logic;
wr_full_o : out std_logic;
almost_full_o : out std_logic;
wr_usedw_o : out std_logic_vector(31 downto 0);
rd_usedw_o : out std_logic_vector(31 downto 0));
end component;
component generic_sync_fifo
generic (
g_width : natural;
g_depth : natural;
g_depth_log2 : natural);
port (
clk_i : in std_logic;
clear_i : in std_logic := '0';
wr_req_i : in std_logic;
d_i : in std_logic_vector (g_width-1 downto 0);
rd_req_i : in std_logic;
q_o : out std_logic_vector (g_width-1 downto 0);
empty_o : out std_logic;
full_o : out std_logic;
usedw_o : out std_logic_vector(g_depth_log2-1 downto 0));
end component;
component generic_ssram_dualport
generic (
g_width : natural;
g_addr_bits : natural;
g_size : natural);
port (
data_i : in std_logic_vector (g_width-1 downto 0);
rd_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
rd_clk_i : in std_logic;
wr_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
wr_clk_i : in std_logic;
wr_en_i : in std_logic := '1';
q_o : out std_logic_vector (g_width-1 downto 0));
end component;
component generic_ssram_dualport_singleclock
generic (
g_width : natural;
g_addr_bits : natural;
g_size : natural;
g_init_file : string := "UNUSED");
port (
data_i : in std_logic_vector (g_width-1 downto 0);
clk_i : in std_logic;
rd_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
wr_addr_i : in std_logic_vector (g_addr_bits-1 downto 0);
wr_en_i : in std_logic := '1';
q_o : out std_logic_vector (g_width-1 downto 0));
end component;
component alt_clock_divider
port (
inclk0 : in std_logic := '0';
......@@ -105,15 +32,6 @@ package platform_specific is
q_o : out std_logic_vector(g_width_out-1 downto 0));
end component;
component generic_clock_mux3
port (
clk_sel_i : in std_logic_vector(1 downto 0);
inclk0_i : in std_logic;
inclk1_i : in std_logic;
inclk2_i : in std_logic;
outclk_o : out std_logic);
end component;
end platform_specific;
-------------------------------------------------------------------------------
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