add dac_sel for new hardware and add some modifications from wrslj.

change g_reverse_dmtds from true to false

add dac_sel for new hardware and add some modifications from wrslj.
change g_reverse_dmtds from true to false
0b26cfb9 · li hongming · 4d68cb12 · 0b26cfb9 · 0b26cfb9 · 0352a53d
Commit 0b26cfb9 authored Jun 10, 2023 by li hongming
12 changed files
--- a/.gitignore
+++ b/.gitignore
@@ -13,3 +13,5 @@ fifo_generator_v6_1
 build_wb.sh
 doc/
 synthesis_descriptor.vhd
+*.en
+gw_ver_pkg.vhd
--- a/Manifest.py
+++ b/Manifest.py
@@ -5,8 +5,8 @@ modules = { "local" : [
 				"modules/wrsw_tru",
 				"modules/wrsw_tatsu",
 				"modules/wrsw_pstats",
-    				"modules/wrsw_hwiu",
-    				"modules/wrsw_watchdog",
+				"modules/wrsw_hwiu",
+				"modules/wrsw_watchdog",
 				"platform/virtex6/chipscope",
 				"platform/xilinx",
 				"ip_cores/wr-cores",

--- a/general-cores @ 0352a53d
+++ b/general-cores @ 0352a53d
-Subproject commit dcc7cc33ffa3bce1a9a3da9ea317e3c768830398
+Subproject commit 0352a53d65a7a2468a6141f860df1f014ea1a346
--- a/wr-cores @ 9df7bfbf
+++ b/wr-cores @ 9df7bfbf
-Subproject commit 8299d657c0f7628312280b6f3911e4b224a6b895
+Subproject commit 9df7bfbfcf57cf6666fd2659a74f5bdcb79a7632
--- a/modules/wrsw_hwiu/gw_ver_pkg.vhd
+++ b/modules/wrsw_hwiu/gw_ver_pkg.vhd
-library ieee;
-use ieee.std_logic_1164.all;
--generated automatically by gen_ver.py script--
-package hwver_pkg is
-constant c_build_date : std_logic_vector(31 downto 0) := x"0e051400";
-constant c_switch_hdl_ver : std_logic_vector(31 downto 0) := x"092bce2d";
-constant c_gencores_ver : std_logic_vector(31 downto 0) := x"0dcc7cc3";
-constant c_wrcores_ver : std_logic_vector(31 downto 0) := x"08299d65";
-end package;
--- a/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
+++ b/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
@@ -85,6 +85,7 @@ entity wrsw_rt_subsystem is
    dac_main_sync_n_o : out std_logic;
    dac_main_sclk_o   : out std_logic;
    dac_main_data_o   : out std_logic;
+    dac_sel_i         : in  std_logic_vector(2 downto 0);

    -- Debug UART
    uart_txd_o : out std_logic;
@@ -238,7 +239,7 @@ architecture rtl of wrsw_rt_subsystem is

 begin  -- rtl

-  clk_rx_vec(g_num_rx_clocks-1 downto 0)         <= clk_rx_i;
+  clk_rx_vec(g_num_rx_clocks-1 downto 0) <= clk_rx_i;

  cnx_slave_in(c_MASTER_CPU) <= wb_i;
  wb_o                       <= cnx_slave_out(c_MASTER_CPU);
@@ -316,7 +317,7 @@ begin  -- rtl
      U_Sampler: entity work.dmtd_sampler
      generic map (
        g_divide_input_by_2 => false,
-        g_reverse           => true)
+        g_reverse           => false)
      port map (
        clk_in_i      => clk_rx_vec(I),
        clk_dmtd_i    => clk_dmtd_i,
@@ -333,7 +334,7 @@ begin  -- rtl
      g_num_ref_inputs         => g_num_rx_clocks,
      g_num_outputs            => 1,
      g_num_exts               => g_num_ext_clks,
-      g_reverse_dmtds          => true,
+      g_reverse_dmtds          => false,
      g_divide_input_by_2      => false,
      g_with_debug_fifo        => true,
      g_ref_clock_rate         => 62500000,
@@ -498,6 +499,7 @@ begin  -- rtl
    port map (
      clk_i         => clk_sys_i,
      rst_n_i       => rst_sys_n_i,
+      dac_sel_i     => dac_sel_i,
      value_i       => dac_out_data,
      cs_sel_i      => "1",
      load_i        => dac_out_load,
@@ -519,6 +521,7 @@ begin  -- rtl
      cs_sel_i      => "1",
      load_i        => dac_dmtd_load,
      sclk_divsel_i => "010",
+      dac_sel_i     => dac_sel_i,
      dac_cs_n_o(0) => dac_helper_sync_n_o,
      dac_sclk_o    => dac_helper_sclk_o,
      dac_sdata_o   => dac_helper_data_o);

--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -82,7 +82,10 @@ entity scb_top_bare is
    -- Programmable aux clock (from the AD9516 PLL output QDRII_200CLK). Used
    -- for re-phasing the 10 MHz input as well as clocking the 
    clk_aux_i : in std_logic;
-
+    
+    -- External 10MHz clock input
+    clk_ext_i     : in  std_logic;
+    -- External 62.5MHz clock input (from 10MHz)
    clk_ext_mul_i	        :	in std_logic_vector(1 downto 0);
    clk_ext_mul_locked_i	:	in std_logic;

@@ -117,12 +120,12 @@ entity scb_top_bare is
    dac_main_sync_n_o : out std_logic;
    dac_main_sclk_o   : out std_logic;
    dac_main_data_o   : out std_logic;
- 
+    dac_sel_i         : in  std_logic_vector(2 downto 0);
+
    -------------------------------------------------------------------------------
    -- AD9516 PLL Control signals
    -------------------------------------------------------------------------------    
-
-    pll_status_i  : in  std_logic;
+    -- pll_status_i  : in  std_logic;
    pll_mosi_o    : out std_logic;
    pll_miso_i    : in  std_logic;
    pll_sck_o     : out std_logic;
@@ -554,7 +557,7 @@ begin

  U_sync_rst_ext : gc_sync_ffs
    port map (
-      clk_i    => pll_status_i,
+      clk_i    => clk_ext_i,
      rst_n_i  => '1',
      data_i   => sys_rst_n_i,
      synced_o => rst_ext_n);
@@ -624,7 +627,7 @@ begin
      clk_dmtd_i          => clk_dmtd_i,
      clk_rx_i            => clk_rx_vec,
      clk_rx_sampled_i    => clk_rx_sampled_vec,
-      clk_ext_i           => pll_status_i,  -- FIXME: UGLY HACK
+      clk_ext_i           => clk_ext_i,
      clk_ext_mul_i       => clk_ext_mul_i,
      clk_ext_mul_locked_i => clk_ext_mul_locked_i,
      clk_aux_p_o         => clk_aux_p_o,
@@ -644,6 +647,7 @@ begin
      dac_main_sync_n_o   => dac_main_sync_n,
      dac_main_sclk_o     => dac_main_sclk,
      dac_main_data_o     => dac_main_data,
+      dac_sel_i           => dac_sel_i,
      uart_txd_o          => uart_txd_o,
      uart_rxd_i          => uart_rxd_i,


--- a/top/bare_top/scb_top_sim.vhd
+++ b/top/bare_top/scb_top_sim.vhd
@@ -202,6 +202,7 @@ begin  -- rtl
      dac_main_sync_n_o   => dac_main_sync_n_o,
      dac_main_sclk_o     => dac_main_sclk_o,
      dac_main_data_o     => dac_main_data_o,
+      dac_sel_i           => "111",
      pll_status_i        => pll_status_i,
      pll_mosi_o          => pll_mosi_o,
      pll_miso_i          => pll_miso_i,

--- a/top/bare_top/wrsw_components_pkg.vhd
+++ b/top/bare_top/wrsw_components_pkg.vhd
@@ -235,6 +235,7 @@ package wrsw_components_pkg is
      dac_main_sync_n_o   : out std_logic;
      dac_main_sclk_o     : out std_logic;
      dac_main_data_o     : out std_logic;
+      dac_sel_i           : in  std_logic_vector(2 downto 0);
      uart_txd_o          : out std_logic;
      uart_rxd_i          : in  std_logic;
      pps_p_o             : out std_logic;

--- a/top/bare_top/wrsw_top_pkg.vhd
+++ b/top/bare_top/wrsw_top_pkg.vhd
@@ -275,6 +275,7 @@ package wrsw_top_pkg is
      dac_main_sync_n_o   : out std_logic;
      dac_main_sclk_o     : out std_logic;
      dac_main_data_o     : out std_logic;
+      dac_sel_i           : in  std_logic_vector(2 downto 0);
      uart_txd_o          : out std_logic;
      uart_rxd_i          : in  std_logic;
      pps_csync_o         : out std_logic;
@@ -348,6 +349,7 @@ package wrsw_top_pkg is
      clk_ref_i           : in  std_logic;
      clk_dmtd_i          : in  std_logic;
      clk_aux_i           : in  std_logic;
+      clk_ext_i           : in  std_logic;
      clk_ext_mul_i       : in  std_logic := '0';
      clk_ext_mul_locked_i : in std_logic_vector(1 downto 0) := (others=>'0');
      clk_sys_o           : out std_logic;
@@ -362,6 +364,7 @@ package wrsw_top_pkg is
      dac_main_sync_n_o   : out std_logic;
      dac_main_sclk_o     : out std_logic;
      dac_main_data_o     : out std_logic;
+      dac_sel_i           : in  std_logic_vector(2 downto 0);
      ljd_dac_main_sync_n_o : out std_logic;
      ljd_dac_main_sclk_o   : out std_logic;
      ljd_dac_main_data_o   : out std_logic;
@@ -379,7 +382,7 @@ package wrsw_top_pkg is
      ljd_pll_sync_n_o      : out std_logic;
      ljd_pll_reset_n_o     : out std_logic;
      ljd_pll_locked_i      : in  std_logic;
-      pll_status_i        : in  std_logic;
+      -- pll_status_i        : in  std_logic;
      pll_mosi_o          : out std_logic;
      pll_miso_i          : in  std_logic;
      pll_sck_o           : out std_logic;

--- a/top/scb_18ports/scb_top_synthesis.ucf
+++ b/top/scb_18ports/scb_top_synthesis.ucf
@@ -10,6 +10,7 @@ NET "fpga_clk_ref_n_i"  LOC=H9;
 NET "fpga_clk_dmtd_p_i"  LOC=L23; 
 NET "fpga_clk_dmtd_n_i"  LOC=M22;

+NET "clk_ext_i"   LOC=K13;
 NET "clk_aux_p_o" LOC=B20;
 NET "clk_aux_n_o" LOC=C19;

@@ -74,8 +75,7 @@ NET "cpu_addr_i<3>" LOC="E33";
 NET "cpu_addr_i<2>" LOC="J27";
 NET "cpu_addr_i<1>" LOC="G31";
 NET "cpu_addr_i<0>" LOC="D32";
-#NET "cpu_addr_i<1>" LOC="H30";
-#NET "cpu_addr_i<0>" LOC="J30";
+
 NET "cpu_data_b<31>" LOC="T26";
 NET "cpu_data_b<30>" LOC="R28";
 NET "cpu_data_b<29>" LOC="R29";
@@ -109,11 +109,10 @@ NET "cpu_data_b<2>" LOC="H33";
 NET "cpu_data_b<1>" LOC="J26";
 NET "cpu_data_b<0>" LOC="A33"; 

-
 NET "pps_i" LOC="J25";
+NET "pps_o" LOC="U23";
 NET "ppsin_term_o" LOC="AL34";
 NET "ppsin_term_o" IOSTANDARD="LVCMOS25";
-NET "pps_o" LOC="U23";

 NET "dac_helper_sync_n_o" LOC="AD17";
 NET "dac_helper_sclk_o" LOC="AC15";
@@ -122,18 +121,21 @@ NET "dac_main_sync_n_o" LOC="AM17";
 NET "dac_main_sclk_o"  LOC="AN17";
 NET "dac_main_data_o" LOC="AP17";

+NET "dac_sel_i[0]" LOC="T24";
+NET "dac_sel_i[1]" LOC="T23";
+NET "dac_sel_i[2]" LOC="AC23";
+
+NET "pll_cs_n_o" LOC="AK18";    # PLL_CS
+NET "pll_sck_o"  LOC="AE16";    # PLL_SCLK
+NET "pll_mosi_o"  LOC="AH19";   # PLL_SDI
+NET "pll_miso_i"  LOC="AJ19";   # PLL_SDO 
+NET "pll_reset_n_o" LOC="AL16"; # PLL_RESET
+NET "pll_sync_n_o" LOC="AG18";  # PLL_SYNC
+
 NET "ljd_dac_main_sync_n_o" LOC = AH32;
 NET "ljd_dac_main_sclk_o" LOC = AK32;
 NET "ljd_dac_main_data_o" LOC = AK33;

-NET "pll_cs_n_o" LOC="AK18";  
-NET "pll_sck_o"  LOC="AE16";  
-NET "pll_mosi_o"  LOC="AH19";  
-NET "pll_miso_i"  LOC="AJ19";  
-NET "pll_reset_n_o" LOC="AL16";
-NET "pll_status_i" LOC="K13";
-NET "pll_sync_n_o" LOC="AG18";
-
 NET "ljd_pll_cs_n_o" LOC = AD27;
 NET "ljd_pll_sck_o" LOC = AD26;
 NET "ljd_pll_mosi_o" LOC = AE27;
@@ -145,8 +147,8 @@ NET "ljd_pll_sync_n_o" LOC = AJ34;
 NET "uart_txd_o" LOC="E11";
 NET "uart_rxd_i" LOC="D11";

-NET "clk_en_o" LOC="AD16";
-NET "clk_sel_o" LOC="AK17";
+NET "clk_en_o" LOC="AD16";    # CLK_EN
+NET "clk_sel_o" LOC="AK17";   # CLK1_SEL

 ### GTX PORTS - reversed to match MB port ordering ###
 NET "gtx0_3_clk_n_i" LOC="AK5";
@@ -179,7 +181,6 @@ NET "gtx16_19_clk_p_i" LOC="H6";
 NET "gtx16_19_clk_n_i" IOSTANDARD="LVPECL_25";
 NET "gtx16_19_clk_p_i" IOSTANDARD="LVPECL_25";

-    
 NET "gtx_rxp_i[17]" LOC="AP5"; # gtx0
 NET "gtx_rxn_i[17]" LOC="AP6";
 NET "gtx_txp_o[17]" LOC="AP1"; 
@@ -197,79 +198,66 @@ NET "gtx_txn_o[15]" LOC="AM2";

 NET "gtx_rxp_i[14]" LOC="AJ3";
 NET "gtx_rxn_i[14]" LOC="AJ4";
-
 NET "gtx_txp_o[14]" LOC="AK1";
 NET "gtx_txn_o[14]" LOC="AK2";

 NET "gtx_rxp_i[13]" LOC="AG3";
 NET "gtx_rxn_i[13]" LOC="AG4";
-
 NET "gtx_txp_o[13]" LOC="AH1";
 NET "gtx_txn_o[13]" LOC="AH2";

 NET "gtx_rxp_i[12]" LOC="AF5";
 NET "gtx_rxn_i[12]" LOC="AF6";
-
 NET "gtx_txp_o[12]" LOC="AF1";
 NET "gtx_txn_o[12]" LOC="AF2";

 NET "gtx_rxp_i[11]" LOC="AE3";
 NET "gtx_rxn_i[11]" LOC="AE4";
-
 NET "gtx_txp_o[11]" LOC="AD1";
 NET "gtx_txn_o[11]" LOC="AD2";

 NET "gtx_rxp_i[10]" LOC="AC3";
 NET "gtx_rxn_i[10]" LOC="AC4";
-
 NET "gtx_txp_o[10]" LOC="AB1";
 NET "gtx_txn_o[10]" LOC="AB2";

 NET "gtx_rxp_i[9]" LOC="AA3";
 NET "gtx_rxn_i[9]" LOC="AA4";
-
 NET "gtx_txp_o[9]" LOC="Y1";
 NET "gtx_txn_o[9]" LOC="Y2";

 NET "gtx_rxp_i[8]" LOC="W3";
 NET "gtx_rxn_i[8]" LOC="W4";
-
 NET "gtx_txp_o[8]" LOC="V1";
 NET "gtx_txn_o[8]" LOC="V2";

 NET "gtx_rxp_i[7]" LOC="U3";
 NET "gtx_rxn_i[7]" LOC="U4";
-
 NET "gtx_txp_o[7]" LOC="T1";
 NET "gtx_txn_o[7]" LOC="T2";

 NET "gtx_rxp_i[6]" LOC="R3";
 NET "gtx_rxn_i[6]" LOC="R4";
-
 NET "gtx_txp_o[6]" LOC="P1";
 NET "gtx_txn_o[6]" LOC="P2";

 NET "gtx_rxp_i[5]" LOC="N3";
 NET "gtx_rxn_i[5]" LOC="N4";
-
 NET "gtx_txp_o[5]" LOC="M1";
 NET "gtx_txn_o[5]" LOC="M2";

 NET "gtx_rxp_i[4]" LOC="L3";
 NET "gtx_rxn_i[4]" LOC="L4";
-
 NET "gtx_txp_o[4]" LOC="K1";
 NET "gtx_txn_o[4]" LOC="K2";

 NET "gtx_rxp_i[3]" LOC="K5"; #gtx14
 NET "gtx_rxn_i[3]" LOC="K6";
-
 NET "gtx_txp_o[3]" LOC="H1";
 NET "gtx_txn_o[3]" LOC="H2";

 NET "gtx_rxp_i[2]" LOC="J3"; # gtx15
 NET "gtx_rxn_i[2]" LOC="J4";
-
 NET "gtx_txp_o[2]" LOC="F1";
 NET "gtx_txn_o[2]" LOC="F2";

@@ -289,26 +277,39 @@ NET "led_act_o[0]" LOC="AE33";
 NET "led_act_o[1]" LOC="AE34";  
 NET "led_act_o[2]" LOC="AB30";  
 NET "led_act_o[3]" LOC="AC30";  
-
 NET "led_act_o[4]" LOC="AA26";  
 NET "led_act_o[5]" LOC="AA25";  
 NET "led_act_o[6]" LOC="AB27";  
 NET "led_act_o[7]" LOC="AC27";  
-
 NET "led_act_o[8]" LOC="AD29";  
 NET "led_act_o[9]" LOC="AE31";  
 NET "led_act_o[10]" LOC="AA29";  
 NET "led_act_o[11]" LOC="AA30";  
-
 NET "led_act_o[12]" LOC="AC29";  
 NET "led_act_o[13]" LOC="AC32";  
 NET "led_act_o[14]" LOC="AD31";  
-
 NET "led_act_o[15]" LOC="AE32";
 NET "led_act_o[16]" LOC="AC28";
 NET "led_act_o[17]" LOC="AG33";

-
+#NET "link_los_i[0]" LOC="AF34";  
+#NET "link_los_i[1]" LOC="AA31";  
+#NET "link_los_i[2]" LOC="AD32";  
+#NET "link_los_i[3]" LOC="AA28";  
+#NET "link_los_i[4]" LOC="AD34";  
+#NET "link_los_i[5]" LOC="AB25";  
+#NET "link_los_i[6]" LOC="AC33";  
+#NET "link_los_i[7]" LOC="AB28";  
+#NET "link_los_i[8]" LOC="AC34";  
+#NET "link_los_i[9]" LOC="Y26";  
+#NET "link_los_i[10]" LOC="AB33";  
+#NET "link_los_i[11]" LOC="AB31";  
+#NET "link_los_i[12]" LOC="AB32";  
+#NET "link_los_i[13]" LOC="AD30";  
+#NET "link_los_i[14]" LOC="AA34";  
+#NET "link_los_i[15]" LOC="AF33";
+#NET "link_los_i[16]" LOC="AA33";
+#NET "link_los_i[17]" LOC="AB26";

 NET "mbl_scl_b[0]" LOC="AF31"; 
 NET "mbl_sda_b[0]" LOC="AG32"; 
@@ -319,15 +320,16 @@ NET "clk_dmtd_divsel_o" LOC="AN15";
 NET "mb_fan1_pwm_o" LOC="C12";
 NET "mb_fan2_pwm_o" LOC="D12";

-
-#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/20
-#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/22
-
 NET "fpga_clk_25mhz_n_i" TNM_NET = fpga_clk_25mhz_n_i;
 TIMESPEC TS_fpga_clk_25mhz_n_i = PERIOD "fpga_clk_25mhz_n_i" 40 ns HIGH 50%;
 NET "fpga_clk_25mhz_p_i" TNM_NET = fpga_clk_25mhz_p_i;
 TIMESPEC TS_fpga_clk_25mhz_p_i = PERIOD "fpga_clk_25mhz_p_i" 40 ns HIGH 50%;

+NET "ljd_clk_62mhz_p_i" TNM_NET = "ljd_clk_62mhz_p_i";
+TIMESPEC TS_ljd_clk_62mhz_p_i = PERIOD "ljd_clk_62mhz_p_i" 16 ns HIGH 50 %;
+NET "ljd_clk_62mhz_n_i" TNM_NET = "ljd_clk_62mhz_n_i";
+TIMESPEC TS_ljd_clk_62mhz_n_i = PERIOD "ljd_clk_62mhz_n_i" 16 ns HIGH 50 %;
+
 NET "fpga_clk_dmtd_n_i" TNM_NET = fpga_clk_dmtd_n_i;
 TIMESPEC TS_fpga_clk_dmtd_n_i = PERIOD "fpga_clk_dmtd_n_i" 16 ns HIGH 50%;
 NET "fpga_clk_dmtd_p_i" TNM_NET = fpga_clk_dmtd_p_i;
@@ -338,20 +340,14 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
 NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
 TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;

-NET "ljd_clk_62mhz_p_i" TNM_NET = "ljd_clk_62mhz_p_i";
-TIMESPEC TS_ljd_clk_62mhz_p_i = PERIOD "ljd_clk_62mhz_p_i" 16 ns HIGH 50 %;
-NET "ljd_clk_62mhz_n_i" TNM_NET = "ljd_clk_62mhz_n_i";
-TIMESPEC TS_ljd_clk_62mhz_n_i = PERIOD "ljd_clk_62mhz_n_i" 16 ns HIGH 50 %;
-
 NET "ext_clk_10mhz_p_i" TNM_NET = "ext_clk_10mhz_p_i";
 TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %;
 NET "ext_clk_10mhz_n_i" TNM_NET = "ext_clk_10mhz_n_i";
 TIMESPEC TS_ext_clk_10mhz_n_i = PERIOD "ext_clk_10mhz_n_i" 100 ns HIGH 50 %;

-NET "pll_status_i" TNM_NET = "pll_status_i";
-TIMESPEC TS_pll_status_i = PERIOD "pll_status_i" 100 ns HIGH 50 %;
+NET "clk_ext_i" TNM_NET = "fpga_clk_10mhz_i";
+TIMESPEC TS_fpga_clk_10mhz_i = PERIOD "fpga_clk_10mhz_i" 100 ns HIGH 50 %;

-#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19
 NET "gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
 NET "gen_phys[1].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
 NET "gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
@@ -376,7 +372,6 @@ NET "gtx0_3_clk_n_i" TNM_NET = gtx0_3_clk_n_i;
 TIMESPEC TS_gtx0_3_clk_n_i = PERIOD "gtx0_3_clk_n_i" 8 ns HIGH 50%;
 NET "gtx0_3_clk_p_i" TNM_NET = gtx0_3_clk_p_i;
 TIMESPEC TS_gtx0_3_clk_p_i = PERIOD "gtx0_3_clk_p_i" 8 ns HIGH 50%;
-
 NET "gtx4_7_clk_n_i" TNM_NET = gtx4_7_clk_n_i;
 TIMESPEC TS_gtx4_7_clk_n_i = PERIOD "gtx4_7_clk_n_i" 8 ns HIGH 50%;
 NET "gtx4_7_clk_p_i" TNM_NET = gtx4_7_clk_p_i;
@@ -409,276 +404,125 @@ AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4;
 AREA_GROUP "pblock_ext_dmtd_2" GROUP=CLOSED;
 AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;

-#NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
-#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/04/25
-#INST "cmp_wb_cpu_bridge/gen_sync_chains_nosim.sync_ffs_wr/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[1].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[2].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[3].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[4].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[5].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[6].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[7].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[8].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[9].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[10].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[11].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[12].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[13].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/rx_done_gen/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_f/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_tx_r/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_EP_TSU/tx_done_gen/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_cal_crst_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_rx_cal_stat_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_tx_cal_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_Rx_Path/U_early_addr_match/U_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[14].U_Endpoint_X/U_Wrapped_Endpoint/U_WB_SLAVE/ep_tscr_cs_done_sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[15].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[15].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[15].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[15].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[15].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[15].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[16].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[16].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[16].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[16].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_an_tx_en/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[16].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_busy_o/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[16].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_TX_PCS/U_sync_pcs_error_o/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[17].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_idle_match/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[17].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_enable/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[17].U_Endpoint_X/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_16bit.U_RX_PCS/U_sync_an_rx_ready/sync0" TNM = Ignore_sync_ffs;
@@ -690,11 +534,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_cr_cnt_e
 INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_cr_cnt_rst_sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_cr_cnt_set_sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/U_RT_Subsystem/U_PPS_Gen/WRAPPED_PPSGEN/Uwb_slave/ppsg_escr_pps_valid_sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_bb_detector.U_BB_Detect/sync_ffs_phase_p/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_bb_detector.U_BB_Detect/U_Detect_Ref_Pulses/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_bb_detector.U_sync_ffs_sync_done/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_bb_detector.U_sync_ffs_sync_en/sync0" TNM = Ignore_sync_ffs;
-#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
@@ -714,7 +554,6 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;

-#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2019/06/18
 INST "gen_phys[0].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
 INST "gen_phys[0].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
 INST "gen_phys[1].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
@@ -739,11 +578,7 @@ INST "gen_phys[10].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
 INST "gen_phys[10].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
 INST "gen_phys[11].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
 INST "gen_phys[11].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
-TIMESPEC TS_ignore1 = FROM Ignore_DMTD TIG;
-TIMESPEC TS_ignore2 = TO Ignore_DMTD TIG;
-TIMESPEC TS_ignore3 = FROM Ignore_sync_ffs TIG;
-TIMESPEC TS_ignore4 = TO Ignore_sync_ffs TIG;
-#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/04/25
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -766,6 +601,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -788,6 +624,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -810,6 +647,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -832,6 +670,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -854,6 +693,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -876,6 +716,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -898,6 +739,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -920,6 +762,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -942,6 +785,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -964,6 +808,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -986,6 +831,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -1008,6 +854,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -1030,6 +877,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -1052,6 +900,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -1074,6 +923,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -1096,6 +946,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -1118,6 +969,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
@@ -1163,6 +1015,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1185,6 +1038,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1207,6 +1061,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1229,6 +1084,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1251,6 +1107,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1273,6 +1130,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1295,6 +1153,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1317,6 +1176,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1339,6 +1199,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1361,6 +1222,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMT
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1383,6 +1245,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1405,6 +1268,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1427,6 +1291,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1449,6 +1314,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1471,6 +1337,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1493,6 +1360,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1515,6 +1383,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/tag_o_19" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
+
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
@@ -1538,23 +1407,6 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DM
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/tag_o_20" TNM = DMTD_TAG_O;
 INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;

-#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/04/25
-TIMESPEC TS_ignore8 = FROM "fpga_clk_ref_p_i" TO "phy_rx_clocks" 20ns DATAPATHONLY;
-TIMESPEC TS_ignore9 = FROM "phy_rx_clocks" TO "fpga_clk_ref_p_i" 20ns DATAPATHONLY;
-TIMESPEC TS_ignore18 = FROM "fpga_clk_dmtd_p_i" TO "phy_rx_clocks" 20ns DATAPATHONLY;
-TIMESPEC TS_ignore19 = FROM "phy_rx_clocks" TO "fpga_clk_dmtd_p_i" 20ns DATAPATHONLY;
-TIMESPEC TS_ignore38 = FROM "fpga_clk_ref_p_i" TO "fpga_clk_dmtd_p_i" 20ns DATAPATHONLY;
-TIMESPEC TS_ignore39 = FROM "fpga_clk_dmtd_p_i" TO "fpga_clk_ref_p_i" 20ns DATAPATHONLY;
-
-TIMESPEC TS_ignore40 = FROM "clk_sys" TO "fpga_clk_dmtd_p_i" 20ns DATAPATHONLY;
-TIMESPEC TS_ignore41 = FROM "fpga_clk_dmtd_p_i" TO "clk_sys" 20ns DATAPATHONLY;
-TIMESPEC TS_ignore42 = FROM "fpga_clk_ref_p_i" TO "clk_sys" 20ns DATAPATHONLY;
-TIMESPEC TS_ignore43 = FROM "clk_sys" TO "fpga_clk_ref_p_i" 20ns DATAPATHONLY;
-TIMESPEC TS_ignore44 = FROM "clk_sys" TO "phy_rx_clocks" 20ns DATAPATHONLY;
-TIMESPEC TS_ignore45 = FROM "phy_rx_clocks" TO "clk_sys" 20ns DATAPATHONLY;
-
-#TIMESPEC TS_dmtd_input = FROM "DMTD_div_clks" TO "FFS" 0.5 ns DATAPATHONLY;
-#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2013/11/06
 NET "gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin;
 NET "gen_phys[1].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[1].gen_lp.U_PHY/rx_rec_clk_bufin;
 NET "gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin;
@@ -1593,10 +1445,6 @@ TIMESPEC TS_gen_phys_15__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[15].gen_no_lp
 TIMESPEC TS_gen_phys_16__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[16].gen_no_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
 TIMESPEC TS_gen_phys_17__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[17].gen_no_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;

-#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17
-TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
-TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY;
-#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2019/07/04
 NET "gen_phys[0].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[0].gen_lp.U_PHY/tx_out_clk_buf;
 TIMESPEC TS_gen_phys_0__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[0].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
 NET "gen_phys[1].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[1].gen_lp.U_PHY/tx_out_clk_buf;
@@ -1621,3 +1469,24 @@ NET "gen_phys[10].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[10].gen_lp.U_P
 TIMESPEC TS_gen_phys_10__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[10].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
 NET "gen_phys[11].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[11].gen_lp.U_PHY/tx_out_clk_buf;
 TIMESPEC TS_gen_phys_11__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[11].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
+
+TIMESPEC TS_ignore1 = FROM Ignore_DMTD TIG;
+TIMESPEC TS_ignore2 = TO Ignore_DMTD TIG;
+TIMESPEC TS_ignore3 = FROM Ignore_sync_ffs TIG;
+TIMESPEC TS_ignore4 = TO Ignore_sync_ffs TIG;
+
+TIMESPEC TS_ignore8      = FROM "fpga_clk_ref_p_i" TO "phy_rx_clocks" 20ns DATAPATHONLY;
+TIMESPEC TS_ignore9      = FROM "phy_rx_clocks" TO "fpga_clk_ref_p_i" 20ns DATAPATHONLY;
+TIMESPEC TS_ignore18     = FROM "fpga_clk_dmtd_p_i" TO "phy_rx_clocks" 20ns DATAPATHONLY;
+TIMESPEC TS_ignore19     = FROM "phy_rx_clocks" TO "fpga_clk_dmtd_p_i" 20ns DATAPATHONLY;
+TIMESPEC TS_ignore38     = FROM "fpga_clk_ref_p_i" TO "fpga_clk_dmtd_p_i" 20ns DATAPATHONLY;
+TIMESPEC TS_ignore39     = FROM "fpga_clk_dmtd_p_i" TO "fpga_clk_ref_p_i" 20ns DATAPATHONLY;
+TIMESPEC TS_ignore40     = FROM "clk_sys" TO "fpga_clk_dmtd_p_i" 20ns DATAPATHONLY;
+TIMESPEC TS_ignore41     = FROM "fpga_clk_dmtd_p_i" TO "clk_sys" 20ns DATAPATHONLY;
+TIMESPEC TS_ignore42     = FROM "fpga_clk_ref_p_i" TO "clk_sys" 20ns DATAPATHONLY;
+TIMESPEC TS_ignore43     = FROM "clk_sys" TO "fpga_clk_ref_p_i" 20ns DATAPATHONLY;
+TIMESPEC TS_ignore44     = FROM "clk_sys" TO "phy_rx_clocks" 20ns DATAPATHONLY;
+TIMESPEC TS_ignore45     = FROM "phy_rx_clocks" TO "clk_sys" 20ns DATAPATHONLY;
+TIMESPEC TS_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
+TIMESPEC TS_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY;
+
--- a/top/scb_18ports/scb_top_synthesis.vhd
+++ b/top/scb_18ports/scb_top_synthesis.vhd
@@ -71,6 +71,9 @@ entity scb_top_synthesis is
    fpga_clk_dmtd_p_i : in std_logic;
    fpga_clk_dmtd_n_i : in std_logic;

+    -- External 10MHz input
+    clk_ext_i    : in  std_logic;
+
    -- 10MHz out clock generated from oserdes
    clk_aux_p_o  : out std_logic;
    clk_aux_n_o  : out std_logic;
@@ -114,12 +117,12 @@ entity scb_top_synthesis is
    dac_main_sclk_o   : out std_logic;
    dac_main_data_o   : out std_logic;

+    dac_sel_i         : in std_logic_vector(2 downto 0);

    -------------------------------------------------------------------------------
    -- AD9516 PLL Control signals
    -------------------------------------------------------------------------------    

-    pll_status_i  : in  std_logic;
    pll_mosi_o    : out std_logic;
    pll_miso_i    : in  std_logic;
    pll_sck_o     : out std_logic;
@@ -262,8 +265,6 @@ architecture Behavioral of scb_top_synthesis is
  -- Clocks
  -------------------------------------------------------------------------------

-
-
  signal clk_sys_startup                        : std_logic;
  signal clk_sys, clk_ref, clk_25mhz , clk_dmtd : std_logic;
  signal pllout_clk_fb                          : std_logic;
@@ -355,6 +356,7 @@ architecture Behavioral of scb_top_synthesis is
      clk_ref_i           : in  std_logic;
      clk_dmtd_i          : in  std_logic;
      clk_aux_i           : in  std_logic;
+      clk_ext_i           : in  std_logic;
      clk_ext_mul_i       : in  std_logic_vector(1 downto 0);
      clk_ext_mul_locked_i: in  std_logic;
      clk_aux_p_o         : out std_logic;
@@ -373,6 +375,7 @@ architecture Behavioral of scb_top_synthesis is
      dac_main_sync_n_o   : out std_logic;
      dac_main_sclk_o     : out std_logic;
      dac_main_data_o     : out std_logic;
+      dac_sel_i           : in  std_logic_vector(2 downto 0);
      ljd_dac_main_sync_n_o : out std_logic;
      ljd_dac_main_sclk_o   : out std_logic;
      ljd_dac_main_data_o   : out std_logic;
@@ -390,7 +393,6 @@ architecture Behavioral of scb_top_synthesis is
      ljd_pll_sync_n_o      : out std_logic;
      ljd_pll_reset_n_o     : out std_logic;
      ljd_pll_locked_i      : in  std_logic;
-      pll_status_i        : in  std_logic;
      pll_mosi_o          : out std_logic;
      pll_miso_i          : in  std_logic;
      pll_sck_o           : out std_logic;
@@ -639,8 +641,8 @@ begin
      I  => fpga_clk_dmtd_p_i,
      IB => fpga_clk_dmtd_n_i);

-  U_swcore_pll: swcore_pll port map  ( clk_sys_i => clk_ref, clk_aux_o => clk_aux); 
- 
+  U_swcore_pll: swcore_pll port map  ( clk_sys_i => clk_ref, clk_aux_o => clk_aux);
+
  U_SYS_PLL : PLL_BASE
    generic map (
      BANDWIDTH          => "OPTIMIZED",
@@ -676,7 +678,7 @@ begin
  -- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
  U_CLKEXT_BUF: IBUFG
    port map (
-      I => pll_status_i,
+      I => clk_ext_i,
      O => clk_ext);

  U_Ext_PLL1: ext_pll_10_to_100
@@ -698,7 +700,7 @@ begin
  clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
  clk_ext_mul_vec(0) <= clk_ext_mul;
  clk_ext_mul_vec(1) <= ljd_clk_62mhz_bufr;
-  
+
  local_reset <= not sys_rst_n_i;
  U_Extend_EXT_Reset: gc_extend_pulse
    generic map (
@@ -873,6 +875,7 @@ begin
      clk_dmtd_i          => clk_dmtd,
      clk_sys_o           => clk_sys,
      clk_aux_i           => clk_aux,
+      clk_ext_i           => clk_10mhz,
      clk_ext_mul_i       => clk_ext_mul_vec,
      clk_ext_mul_locked_i=> clk_ext_mul_locked,
      clk_aux_p_o         => clk_aux_p_o,
@@ -889,6 +892,7 @@ begin
      dac_main_sync_n_o   => dac_main_sync_n_o,
      dac_main_sclk_o     => dac_main_sclk_o,
      dac_main_data_o     => dac_main_data_o,
+      dac_sel_i           => dac_sel_i,
      -- Low-jitter daughterboard support
      ljd_dac_main_sync_n_o => ljd_dac_main_sync_n_o,
      ljd_dac_main_sclk_o   => ljd_dac_main_sclk_o,
@@ -908,7 +912,6 @@ begin
      ljd_pll_reset_n_o     => ljd_pll_reset_n_o,
      ljd_pll_locked_i      => ljd_pll_locked_i,

-      pll_status_i        => clk_10mhz,
      pll_mosi_o          => pll_mosi_o,
      pll_miso_i          => pll_miso_i,
      pll_sck_o           => pll_sck_o,