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White Rabbit Switch - Gateware
Commit 0b26cfb9 authored by li hongming's avatar li hongming
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add dac_sel for new hardware and add some modifications from wrslj. 

  change g_reverse_dmtds from true to false
parent 4d68cb12
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Showing with 155 additions and 278 deletions
.gitignore
View file @ 0b26cfb9
......@@ -13,3 +13,5 @@ fifo_generator_v6_1
build_wb.sh
doc/
synthesis_descriptor.vhd
*.en
gw_ver_pkg.vhd
Manifest.py
View file @ 0b26cfb9
......@@ -5,8 +5,8 @@ modules = { "local" : [
"modules/wrsw_tru",
"modules/wrsw_tatsu",
"modules/wrsw_pstats",
"modules/wrsw_hwiu",
"modules/wrsw_watchdog",
"modules/wrsw_hwiu",
"modules/wrsw_watchdog",
"platform/virtex6/chipscope",
"platform/xilinx",
"ip_cores/wr-cores",
......
general-cores @ 0352a53d
Subproject commit dcc7cc33ffa3bce1a9a3da9ea317e3c768830398
Subproject commit 0352a53d65a7a2468a6141f860df1f014ea1a346
wr-cores @ 9df7bfbf
Subproject commit 8299d657c0f7628312280b6f3911e4b224a6b895
Subproject commit 9df7bfbfcf57cf6666fd2659a74f5bdcb79a7632
modules/wrsw_hwiu/gw_ver_pkg.vhd deleted 100644 → 0
View file @ 4d68cb12
library ieee;
use ieee.std_logic_1164.all;
--generated automatically by gen_ver.py script--
package hwver_pkg is
constant c_build_date : std_logic_vector(31 downto 0) := x"0e051400";
constant c_switch_hdl_ver : std_logic_vector(31 downto 0) := x"092bce2d";
constant c_gencores_ver : std_logic_vector(31 downto 0) := x"0dcc7cc3";
constant c_wrcores_ver : std_logic_vector(31 downto 0) := x"08299d65";
end package;
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 0b26cfb9
......@@ -85,6 +85,7 @@ entity wrsw_rt_subsystem is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
dac_sel_i : in std_logic_vector(2 downto 0);
-- Debug UART
uart_txd_o : out std_logic;
......@@ -238,7 +239,7 @@ architecture rtl of wrsw_rt_subsystem is
begin -- rtl
clk_rx_vec(g_num_rx_clocks-1 downto 0) <= clk_rx_i;
clk_rx_vec(g_num_rx_clocks-1 downto 0) <= clk_rx_i;
cnx_slave_in(c_MASTER_CPU) <= wb_i;
wb_o <= cnx_slave_out(c_MASTER_CPU);
......@@ -316,7 +317,7 @@ begin -- rtl
U_Sampler: entity work.dmtd_sampler
generic map (
g_divide_input_by_2 => false,
g_reverse => true)
g_reverse => false)
port map (
clk_in_i => clk_rx_vec(I),
clk_dmtd_i => clk_dmtd_i,
......@@ -333,7 +334,7 @@ begin -- rtl
g_num_ref_inputs => g_num_rx_clocks,
g_num_outputs => 1,
g_num_exts => g_num_ext_clks,
g_reverse_dmtds => true,
g_reverse_dmtds => false,
g_divide_input_by_2 => false,
g_with_debug_fifo => true,
g_ref_clock_rate => 62500000,
......@@ -498,6 +499,7 @@ begin -- rtl
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
dac_sel_i => dac_sel_i,
value_i => dac_out_data,
cs_sel_i => "1",
load_i => dac_out_load,
......@@ -519,6 +521,7 @@ begin -- rtl
cs_sel_i => "1",
load_i => dac_dmtd_load,
sclk_divsel_i => "010",
dac_sel_i => dac_sel_i,
dac_cs_n_o(0) => dac_helper_sync_n_o,
dac_sclk_o => dac_helper_sclk_o,
dac_sdata_o => dac_helper_data_o);
......
top/bare_top/scb_top_bare.vhd
View file @ 0b26cfb9
......@@ -82,7 +82,10 @@ entity scb_top_bare is
-- Programmable aux clock (from the AD9516 PLL output QDRII_200CLK). Used
-- for re-phasing the 10 MHz input as well as clocking the
clk_aux_i : in std_logic;
-- External 10MHz clock input
clk_ext_i : in std_logic;
-- External 62.5MHz clock input (from 10MHz)
clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i : in std_logic;
......@@ -117,12 +120,12 @@ entity scb_top_bare is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
dac_sel_i : in std_logic_vector(2 downto 0);
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -554,7 +557,7 @@ begin
U_sync_rst_ext : gc_sync_ffs
port map (
clk_i => pll_status_i,
clk_i => clk_ext_i,
rst_n_i => '1',
data_i => sys_rst_n_i,
synced_o => rst_ext_n);
......@@ -624,7 +627,7 @@ begin
clk_dmtd_i => clk_dmtd_i,
clk_rx_i => clk_rx_vec,
clk_rx_sampled_i => clk_rx_sampled_vec,
clk_ext_i => pll_status_i, -- FIXME: UGLY HACK
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_aux_p_o => clk_aux_p_o,
......@@ -644,6 +647,7 @@ begin
dac_main_sync_n_o => dac_main_sync_n,
dac_main_sclk_o => dac_main_sclk,
dac_main_data_o => dac_main_data,
dac_sel_i => dac_sel_i,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
......
top/bare_top/scb_top_sim.vhd
View file @ 0b26cfb9
......@@ -202,6 +202,7 @@ begin -- rtl
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
dac_sel_i => "111",
pll_status_i => pll_status_i,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
......
top/bare_top/wrsw_components_pkg.vhd
View file @ 0b26cfb9
......@@ -235,6 +235,7 @@ package wrsw_components_pkg is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
dac_sel_i : in std_logic_vector(2 downto 0);
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
pps_p_o : out std_logic;
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 0b26cfb9
......@@ -275,6 +275,7 @@ package wrsw_top_pkg is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
dac_sel_i : in std_logic_vector(2 downto 0);
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
pps_csync_o : out std_logic;
......@@ -348,6 +349,7 @@ package wrsw_top_pkg is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic_vector(1 downto 0) := (others=>'0');
clk_sys_o : out std_logic;
......@@ -362,6 +364,7 @@ package wrsw_top_pkg is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
dac_sel_i : in std_logic_vector(2 downto 0);
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
......@@ -379,7 +382,7 @@ package wrsw_top_pkg is
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic;
pll_status_i : in std_logic;
-- pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ 0b26cfb9
This diff is collapsed.
top/scb_18ports/scb_top_synthesis.vhd
View file @ 0b26cfb9
......@@ -71,6 +71,9 @@ entity scb_top_synthesis is
fpga_clk_dmtd_p_i : in std_logic;
fpga_clk_dmtd_n_i : in std_logic;
-- External 10MHz input
clk_ext_i : in std_logic;
-- 10MHz out clock generated from oserdes
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
......@@ -114,12 +117,12 @@ entity scb_top_synthesis is
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
dac_sel_i : in std_logic_vector(2 downto 0);
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -262,8 +265,6 @@ architecture Behavioral of scb_top_synthesis is
-- Clocks
-------------------------------------------------------------------------------
signal clk_sys_startup : std_logic;
signal clk_sys, clk_ref, clk_25mhz , clk_dmtd : std_logic;
signal pllout_clk_fb : std_logic;
......@@ -355,6 +356,7 @@ architecture Behavioral of scb_top_synthesis is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
......@@ -373,6 +375,7 @@ architecture Behavioral of scb_top_synthesis is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
dac_sel_i : in std_logic_vector(2 downto 0);
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
......@@ -390,7 +393,6 @@ architecture Behavioral of scb_top_synthesis is
ljd_pll_sync_n_o : out std_logic;
ljd_pll_reset_n_o : out std_logic;
ljd_pll_locked_i : in std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -639,8 +641,8 @@ begin
I => fpga_clk_dmtd_p_i,
IB => fpga_clk_dmtd_n_i);
U_swcore_pll: swcore_pll port map ( clk_sys_i => clk_ref, clk_aux_o => clk_aux);
U_swcore_pll: swcore_pll port map ( clk_sys_i => clk_ref, clk_aux_o => clk_aux);
U_SYS_PLL : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
......@@ -676,7 +678,7 @@ begin
-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
U_CLKEXT_BUF: IBUFG
port map (
I => pll_status_i,
I => clk_ext_i,
O => clk_ext);
U_Ext_PLL1: ext_pll_10_to_100
......@@ -698,7 +700,7 @@ begin
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
clk_ext_mul_vec(0) <= clk_ext_mul;
clk_ext_mul_vec(1) <= ljd_clk_62mhz_bufr;
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
generic map (
......@@ -873,6 +875,7 @@ begin
clk_dmtd_i => clk_dmtd,
clk_sys_o => clk_sys,
clk_aux_i => clk_aux,
clk_ext_i => clk_10mhz,
clk_ext_mul_i => clk_ext_mul_vec,
clk_ext_mul_locked_i=> clk_ext_mul_locked,
clk_aux_p_o => clk_aux_p_o,
......@@ -889,6 +892,7 @@ begin
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
dac_sel_i => dac_sel_i,
-- Low-jitter daughterboard support
ljd_dac_main_sync_n_o => ljd_dac_main_sync_n_o,
ljd_dac_main_sclk_o => ljd_dac_main_sclk_o,
......@@ -908,7 +912,6 @@ begin
ljd_pll_reset_n_o => ljd_pll_reset_n_o,
ljd_pll_locked_i => ljd_pll_locked_i,
pll_status_i => clk_10mhz,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
......
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