A fully parameterized and generic Verilog implementation of the suggested modular switched multi-ported SRAM-based memory, together with previous approaches are provided as open source hardware. A run-in-batch flow manager to simulate and synthesize various designs with various parameters in batch using Altera's ModelSim and Quartus is also provided.
**LICENSE:** BSD 3-Clause ("BSD New" or "BSD Simplified") license.
This package is part of a journal paper submission to:
**ACM Transactions on Reconfigurable Technology and Systems (TRETS); Special Issue on Reconfigurable Components with Source Code.**
***Authors**: Ameer M.S. Abdelhadi and Guy G.F. Lemieux - UBC
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## CAD Tools Requirements ##
This project has been tested intensively using Altera's Design Suite version 14.0 Specifically:
1. Quartus II version 14.0 has been used to synthesize the Verilog implementation
1. ModelSim Altera Edition version 10.0d (modelsim\_ase) has been used to simulate the Verilog implementation.
Furthermore, the run-in-batch synthesis and simulation flow managers have been implemented using C-Shell, hence a /bin/csh should be available in the machine
---
## Files and directories in this package ##
***README:** Read this first!
***LICENSE:** BSD 3-Clause ("BSD New" or "BSD Simplified") license.
***altera.12.0.ubc.csh:** C-shell script: Setup environment variables and Altera 12.0 CAD flow from The University of British Columbia (UBC). Change parameters to your environment if required.
***altera.13.1.ubc.csh:** C-shell script: Setup environment variables and Altera 13.1 CAD flow from The University of British Columbia (UBC).
***altera.14.0.ubc.csh:** C-shell script: Setup environment variables and Altera 14.0 CAD flow from The University of British Columbia (UBC).
***altera.14.0.fab.csh:** C-shell script: Setup environment variables and Altera 14.0 CAD flow from FAbRIC (FPGA Research Infrastructure Cloud); Texas Advanced Computing Center (TACC); UT Austin - https://wikis.utexas.edu/display/fabric/Home
***sim:** C-shell script: A run-in-batch simulation flow manager .
***syn:** C-shell script: A run-in-batch synthesis flow manager.
***config.vh:** Verilog: Generated by 'syn' script, contains design parameters.
***mrram.v:** Verilog: Multiread-RAM based on bank replication using generic dual-ported RAM with optional single-stage or two-stage bypass/ for normal mode ports.
***mrram\_swt.v:** Verilog: Multiread-RAM based on bank replication using generic dual-ported RAM with optional single-stage or two-stage bypass and switched read ports support.
***dpram.v:** Verilog: Generic dual-ported RAM .
***dpram\_bbs.v:** Verilog: Generic dual-ported RAM with optional single-stage or two-stage bypass.
***mpram\_reg.v:** Verilog: Generic register-based multiported-RAM. Reading addresses are registered and old data will be read in case of RAW. Implemented in FF's if the number of reading or writing ports exceeds one.
***mpram\_xor.v:** Verilog: Multiported-RAM based on XOR implementation.
***sim.res:** A list of simulation results, each run in a separate line, including all architectures.
***syn.res:** A list of synthesis results, each run in a separate line, including: frequency, resources usage, and runtime.
***log/:** A directory containing Altera's logs and reports.
***syn.res.example:** Example synthesis results.
***sim.res.example:** Example simulation results.
***log.example.tar.xz:** xz tarball: archived log directory example (for the runs listed in syn.res.example). To extract invoke: tar -xavf log.example.tar.xz
All **.v &**.vh files in this package should be copied into your work directory. Copy the following instantiation into your Verilog design, change parameters and connectivity to fit your design.
.RData(RData) // read data - packed from nRPF fixed & nRPS switched ports - output:[DATW *(nRPF+nRPS)-1:0]
);
```
---
## `sim`: A Run-in-batch Simulation Flow Manager ##
### USAGE: ###
> `./sim <Depth List> <Width List> <#Write Ports List (Fixed-Switched)> <#Read Ports List (Fixed-Switched)> <Bypass List> <#Cycles> [verbose]`
* Use a comma delimited list.
* No spaces.
* May be surrounded by any brackets (), [], {}, or <>.
* RAM depth, data width, and simulation cycles are positive integers.
* Numbers of read and write ports are:
* Pairs of "fixed-switched" port numbers delimited with hyphen "-", or,
* Fixed port number only, if switched ports are not required.
* numbers of read/write ports are integers.
* #switched\_read\_ports < = #fixed\_read\_ports
* Bypassing type is one of: NON, WAW, RAW, or RDW.
* NON: No bypassing logic
* WAW: Allow Write-After-Write
* RAW: new data for Read-after-Write
* RDW: new data for Read-During-Write
* "verbose" is an optional argument; use if verbosed logging is required
### EXAMPLES: ###
*`./sim 1024 32 1-2 2-2 NON 1000000 verbose`
* Simulate 1M cycles of a 1K lines RAM, 32 bits width, 1 fixed / 2 switched write & 2 fixed / 2 switched read ports, no bypassing, verbose logging,
*`./sim 512,1024 8,16,32 2,3,4 1,2,3,4 RAW 1000000`
* Simulate 1M cycles of RAMs with 512 or 1024 lines, 8, 16, or 32 bits width, 2,3, or 4 fixed write ports, 1,2,3, or 4 fixed read ports, with RAW bypass.
The following files and directories will be created after simulation :
* sim.res : A list of simulation results, each run in a separate line, including all design styles.
---
## `syn`: A Run-in-batch Synthesis Flow Manager ##
### USAGE: ###
`./syn <Depth List> <Width List> <#Write Ports List (Fixed-Switched)> <#Read Ports List (Fixed-Switched)> <Bypass List> <Architecture List>`
* Use a comma delimited list.
* No spaces.
* May be surrounded by any brackets (), [], {}, or <>.
* RAM depth, data width, and simulation cycles are positive integers.
* Numbers of read and write ports are:
* Pairs of "fixed-switched" port numbers delimited with hyphen "-", or,
* Fixed port number only, if switched ports are not required.
* numbers of read/write ports are integers.
* #switched\_read\_ports < = #fixed\_read\_ports
* Bypassing type is one of: NON, WAW, RAW, or RDW.
* NON: No bypassing logic
* WAW: Allow Write-After-Write
* RAW: new data for Read-after-Write
* RDW: new data for Read-During-Write
* Architecture is one of: REG, XOR, LVTREG, LVTBIN, or LVT1HT.
-- write_done_o(i) <= '1' when ((write_grant_vec_d0(i) = '1' and tmp_write_end_of_list(i) = '1') or -- end-of-list, one one write, so write_done faster
-- (write_grant_vec_d0(i) = '1' and write_grant_vec_d1(i) = '1' and tmp_write_end_of_list(i) = '0')) else -- normal write, we write two words, it takes longer
-- '0';
-- end generate;
wr_done:foriin0tog_num_ports-1generate
write_done_o(i)<='1'when((write_grant_vec_d0(i)='1'andwrite_next_addr_valid_i(i)='0')or-- end-of-list, one one write, so write_done faster
(write_grant_vec_d0(i)='1'andwrite_grant_vec_d1(i)='1'andwrite_next_addr_valid_i(i)='1'))else-- normal write, we write two words, it takes longer
