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White Rabbit Switch - Gateware
Commit 0f9aee8f authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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pstats: more registers to improve timing

parent 350789e8
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Showing with 13 additions and 4 deletions
modules/wrsw_pstats/port_cntr.vhd
View file @ 0f9aee8f
...@@ -180,10 +180,10 @@ begin ...@@ -180,10 +180,10 @@ begin
events_presub <= events_reg((f_onehot_decode(events_grant)+1)*g_cnt_pw-1 downto f_onehot_decode(events_grant)*g_cnt_pw); events_presub <= events_reg((f_onehot_decode(events_grant)+1)*g_cnt_pw-1 downto f_onehot_decode(events_grant)*g_cnt_pw);
GEN_EVT_CLR: for i in 0 to c_rr_range-1 generate --GEN_EVT_CLR: for i in 0 to c_rr_range-1 generate
events_clr((i+1)*g_cnt_pw-1 downto i*g_cnt_pw) <= events_presub when(cnt_state=WRITE and events_grant(i)='1') else -- events_clr((i+1)*g_cnt_pw-1 downto i*g_cnt_pw) <= events_presub when(cnt_state=WRITE and events_grant(i)='1') else
(others=>'0'); -- (others=>'0');
end generate; --end generate;
mem_adr <= f_onehot_decode(events_grant); mem_adr <= f_onehot_decode(events_grant);
...@@ -195,6 +195,7 @@ begin ...@@ -195,6 +195,7 @@ begin
mem_wr <= '0'; mem_wr <= '0';
events_sub <= (others => '0'); events_sub <= (others => '0');
events_preg <= (others => '0'); events_preg <= (others => '0');
events_clr <= (others=>'0');
else else
...@@ -202,6 +203,7 @@ begin ...@@ -202,6 +203,7 @@ begin
when SEL => when SEL =>
--check each segment of events_i starting from the one pointed by round robin --check each segment of events_i starting from the one pointed by round robin
mem_wr <= '0'; mem_wr <= '0';
events_clr <= (others=>'0');
f_rr_arbitrate(events_ored, events_preg, events_grant); f_rr_arbitrate(events_ored, events_preg, events_grant);
if(or_reduce(events_ored) = '1') then if(or_reduce(events_ored) = '1') then
...@@ -211,6 +213,13 @@ begin ...@@ -211,6 +213,13 @@ begin
end if; end if;
when WRITE => when WRITE =>
for i in 0 to c_rr_range-1 loop
if events_grant(i) = '1' then
events_clr((i+1)*g_cnt_pw-1 downto i*g_cnt_pw) <= events_reg((i+1)*g_cnt_pw-1 downto i*g_cnt_pw);
else
events_clr((i+1)*g_cnt_pw-1 downto i*g_cnt_pw) <= (others=>'0');
end if;
end loop;
events_sub <= events_presub; events_sub <= events_presub;
mem_wr <= '1'; mem_wr <= '1';
cnt_state <= SEL; cnt_state <= SEL;
......
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