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White Rabbit Switch - Gateware
Commit 0fbd4ec0 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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re-organized top modules to have separate GTX-less simulation top core

parent fe1cc0c8
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syn/scb_18ports/Manifest.py 0 → 100644
View file @ 0fbd4ec0
target = "xilinx"
action = "synthesis"
fetchto = "../../ip_cores"
syn_device = "xc6vlx130t"
syn_grade = "-1"
syn_package = "ff1156"
syn_top = "scb_top_synthesis"
syn_project = "test_scb.xise"
modules = { "local" : [ "../../top/scb_18ports" ] }
syn/scb_18ports/test_scb.xise 0 → 100644
View file @ 0fbd4ec0
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top/bare_top/Manifest.py 0 → 100644
View file @ 0fbd4ec0
files = [ "scb_top_bare.vhd", "wb_cpu_bridge.vhd","wrsw_top_pkg.vhd","scb_top_sim.vhd" ];
modules = { "local" : [ "../../" ] };
top/bare_top/scb_top_sim.vhd 0 → 100644
View file @ 0fbd4ec0
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
use work.wrsw_top_pkg.all;
use work.disparity_gen_pkg.all;
entity scb_top_sim is
generic(
g_num_ports : integer := 6
);
port (
sys_rst_n_i : in std_logic; -- global reset
-- Startup 25 MHz clock (from onboard 25 MHz oscillator)
clk_startup_i : in std_logic;
-- 125 MHz timing reference (from the AD9516 PLL output QDRII_CLK)
clk_ref_i : in std_logic;
-- 125+ MHz DMTD offset clock (from the CDCM62001 PLL output DMTDCLK_MAIN)
clk_dmtd_i : in std_logic;
-- 62.5 MHz system clock (from the AD9516 PLL output QDRII_200CLK)
clk_sys_i : in std_logic;
-------------------------------------------------------------------------------
-- Master wishbone bus (from the CPU bridge)
-------------------------------------------------------------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
-------------------------------------------------------------------------------
-- Timing I/O
-------------------------------------------------------------------------------
pps_i : in std_logic;
pps_o : out std_logic;
-- DAC Drive
dac_helper_sync_n_o : out std_logic;
dac_helper_sclk_o : out std_logic;
dac_helper_data_o : out std_logic;
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-------------------------------------------------------------------------------
-- Clock fanout control
-------------------------------------------------------------------------------
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
---------------------------------------------------------------------------
-- GTX ports
---------------------------------------------------------------------------
td_o : out std_logic_vector(18 * g_num_ports-1 downto 0);
rd_i : in std_logic_vector(18 * g_num_ports-1 downto 0);
rbclk_i : in std_logic_vector(g_num_ports-1 downto 0);
led_link_o : out std_logic_vector(g_num_ports-1 downto 0);
led_act_o : out std_logic_vector(g_num_ports-1 downto 0)
);
end scb_top_sim;
architecture rtl of scb_top_sim is
type t_8b10b_disparity_array is array (integer range <>) of t_8b10b_disparity;
signal cur_disp : t_8b10b_disparity_array(g_num_ports-1 downto 0);
signal cpu_wb_in : t_wishbone_slave_in;
signal cpu_wb_out : t_wishbone_slave_out;
signal phys_out : t_phyif_output_array(g_num_ports-1 downto 0);
signal phys_in : t_phyif_input_array(g_num_ports-1 downto 0);
signal cpu_irq_n : std_logic;
begin -- rtl
cpu_wb_in.adr <= wb_adr_i;
cpu_wb_in.dat <= wb_dat_i;
cpu_wb_in.cyc <= wb_cyc_i;
cpu_wb_in.sel <= wb_sel_i;
cpu_wb_in.we <= wb_we_i;
cpu_wb_in.stb <= wb_stb_i;
wb_ack_o <= cpu_wb_out.ack;
wb_stall_o <= cpu_wb_out.stall;
wb_irq_o <= not cpu_irq_n;
wb_dat_o <= cpu_wb_out.dat;
U_Wrapped_SCBCore : scb_top_bare
generic map (
g_num_ports => g_num_ports,
g_simulation => true)
port map (
sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_startup_i,
clk_ref_i => clk_ref_i,
clk_dmtd_i => clk_dmtd_i,
clk_sys_i => clk_sys_i,
cpu_wb_i => cpu_wb_in,
cpu_wb_o => cpu_wb_out,
cpu_irq_n_o => cpu_irq_n,
pps_i => pps_i,
pps_o => pps_o,
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
dac_helper_data_o => dac_helper_data_o,
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
pll_status_i => pll_status_i,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o,
clk_sel_o => clk_sel_o,
phys_o => phys_out,
phys_i => phys_in,
led_link_o => led_link_o,
led_act_o => led_act_o);
gen_phys : for i in 0 to g_num_ports-1 generate
td_o(18 * i + 15 downto 18 * i) <= phys_out(i).tx_data;
td_o(18 * i + 17 downto 18 * i + 16) <= phys_out(i).tx_k;
phys_in(i).ref_clk <= clk_ref_i;
phys_in(i).rx_data <= rd_i(18 * i + 15 downto 18 * i);
phys_in(i).rx_k <= rd_i(18 * i + 17 downto 18 * i + 16);
phys_in(i).rx_clk <= rbclk_i(i);
phys_in(i).tx_enc_err <= '0';
phys_in(i).rx_enc_err <= '0';
p_gen_tx_disparity : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if phys_out(i).rst = '1' then
cur_disp(i) <= RD_MINUS;
else
cur_disp(i) <= f_next_8b10b_disparity16(cur_disp(i), phys_out(i).tx_k, phys_out(i).tx_data);
end if;
end if;
end process;
phys_in(i).tx_disparity <= to_std_logic(cur_disp(i));
end generate gen_phys;
end rtl;
top/scb_6ports/wrsw_components_pkg.vhd → top/bare_top/wrsw_components_pkg.vhd
View file @ 0fbd4ec0
......@@ -7,6 +7,29 @@ use work.wrsw_txtsu_pkg.all;
package wrsw_components_pkg is
-- Output from SCB core to PHY
type t_phyif_output is record
rst : std_logic;
loopen : std_logic;
enable : std_logic;
syncen : std_logic;
tx_data : std_logic_vector(15 downto 0);
tx_k : std_logic_vector(1 downto 0);
end record;
type t_phyif_input is record
tx_disparity : std_logic;
tx_enc_err : std_logic;
rx_data : std_logic_vector(15 downto 0);
rx_clk : std_logic;
rx_k : std_logic_vector(1 downto 0);
rx_enc_err : std_logic;
rx_bitslide : std_logic_vector(4 downto 0);
end record;
type t_phyif_output_array is array(integer range <>) of t_phyif_output;
type t_phyif_input_array is array(integer range <>) of t_phyif_input;
component wb_cpu_bridge
generic (
g_simulation : integer := 0;
......@@ -56,7 +79,7 @@ package wrsw_components_pkg is
component wr_gtx_phy_virtex6
generic (
g_simulation : integer;
g_simulation : integer;
g_use_slave_tx_clock : integer);
port (
clk_ref_i : in std_logic;
......@@ -82,7 +105,8 @@ package wrsw_components_pkg is
component xwr_pps_gen
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
g_address_granularity : t_wishbone_address_granularity;
g_ref_clock_rate : integer);
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
......@@ -181,5 +205,23 @@ package wrsw_components_pkg is
TRIG3 : in std_logic_vector(31 downto 0));
end component;
component xswc_core
generic (
g_swc_num_ports : integer;
g_swc_prio_width : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in_array(g_swc_num_ports-1 downto 0);
snk_o : out t_wrf_sink_out_array(g_swc_num_ports-1 downto 0);
src_i : in t_wrf_source_in_array(g_swc_num_ports-1 downto 0);
src_o : out t_wrf_source_out_array(g_swc_num_ports-1 downto 0);
rtu_rsp_valid_i : in std_logic_vector(g_swc_num_ports - 1 downto 0);
rtu_rsp_ack_o : out std_logic_vector(g_swc_num_ports - 1 downto 0);
rtu_dst_port_mask_i : in std_logic_vector(g_swc_num_ports * g_swc_num_ports - 1 downto 0);
rtu_drop_i : in std_logic_vector(g_swc_num_ports - 1 downto 0);
rtu_prio_i : in std_logic_vector(g_swc_num_ports * g_swc_prio_width - 1 downto 0));
end component;
end wrsw_components_pkg;
top/bare_top/wrsw_top_pkg.vhd 0 → 100644
View file @ 0fbd4ec0
This diff is collapsed.
top/scb_18ports/Manifest.py 0 → 100644
View file @ 0fbd4ec0
files = ["scb_top_synthesis.ucf", "scb_top_synthesis.vhd"];
modules = { "local" : [ "../../", "../bare_top" ] };
top/scb_18ports/scb_top_synthesis.ucf 0 → 100644
View file @ 0fbd4ec0
NET "sys_rst_n_i" LOC="M10";
# CLK
NET "fpga_clk_25mhz_p_i" LOC=K24;
NET "fpga_clk_25mhz_n_i" LOC=K23;
NET "fpga_clk_ref_p_i" LOC=J9;
NET "fpga_clk_ref_n_i" LOC=H9;
NET "fpga_clk_sys_p_i" LOC=A10;
NET "fpga_clk_sys_n_i" LOC=B10;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
#EBI BUS
#NET "cpu_clk_i" LOC="";
NET "cpu_cs_n_i" LOC="H34";
NET "cpu_wr_n_i" LOC="M25";
NET "cpu_rd_n_i" LOC="J31";
NET "cpu_bs_n_i<0>" LOC="J30";
NET "cpu_bs_n_i<1>" LOC="P29";
NET "cpu_bs_n_i<2>" LOC="H30";
NET "cpu_bs_n_i<3>" LOC="J34";
NET "cpu_nwait_o" LOC="R26";
NET "cpu_irq_n_o" LOC="AC24";
NET "cpu_addr_i<18>" LOC="M28";
NET "cpu_addr_i<17>" LOC="M30";
NET "cpu_addr_i<16>" LOC="C32";
NET "cpu_addr_i<15>" LOC="L31";
NET "cpu_addr_i<14>" LOC="L25";
NET "cpu_addr_i<13>" LOC="B33";
NET "cpu_addr_i<12>" LOC="B32";
NET "cpu_addr_i<11>" LOC="C33";
NET "cpu_addr_i<10>" LOC="L26";
NET "cpu_addr_i<9>" LOC="H32";
NET "cpu_addr_i<8>" LOC="G32";
NET "cpu_addr_i<7>" LOC="E32";
NET "cpu_addr_i<6>" LOC="F30";
NET "cpu_addr_i<5>" LOC="D31";
NET "cpu_addr_i<4>" LOC="L28";
NET "cpu_addr_i<3>" LOC="E33";
NET "cpu_addr_i<2>" LOC="J27";
NET "cpu_addr_i<1>" LOC="G31";
NET "cpu_addr_i<0>" LOC="D32";
#NET "cpu_addr_i<1>" LOC="H30";
#NET "cpu_addr_i<0>" LOC="J30";
NET "cpu_data_b<31>" LOC="T26";
NET "cpu_data_b<30>" LOC="R28";
NET "cpu_data_b<29>" LOC="R29";
NET "cpu_data_b<28>" LOC="N34";
NET "cpu_data_b<27>" LOC="P34";
NET "cpu_data_b<26>" LOC="P25";
NET "cpu_data_b<25>" LOC="L34";
NET "cpu_data_b<24>" LOC="R32";
NET "cpu_data_b<23>" LOC="R27";
NET "cpu_data_b<22>" LOC="P27";
NET "cpu_data_b<21>" LOC="P26";
NET "cpu_data_b<20>" LOC="K34";
NET "cpu_data_b<19>" LOC="M31";
NET "cpu_data_b<18>" LOC="R31";
NET "cpu_data_b<17>" LOC="N30";
NET "cpu_data_b<16>" LOC="N25";
NET "cpu_data_b<15>" LOC="L33";
NET "cpu_data_b<14>" LOC="K31";
NET "cpu_data_b<13>" LOC="K29";
NET "cpu_data_b<12>" LOC="K33";
NET "cpu_data_b<11>" LOC="J29";
NET "cpu_data_b<10>" LOC="K32";
NET "cpu_data_b<9>" LOC="M32";
NET "cpu_data_b<8>" LOC="J32";
NET "cpu_data_b<7>" LOC="C34";
NET "cpu_data_b<6>" LOC="K28";
NET "cpu_data_b<5>" LOC="G30";
NET "cpu_data_b<4>" LOC="D34";
NET "cpu_data_b<3>" LOC="B34";
NET "cpu_data_b<2>" LOC="H33";
NET "cpu_data_b<1>" LOC="J26";
NET "cpu_data_b<0>" LOC="A33";
NET "pps_i" LOC="J25";
NET "pps_o" LOC="U23";
NET "dac_helper_sync_n_o" LOC="AD17";
NET "dac_helper_sclk_o" LOC="AC15";
NET "dac_helper_data_o" LOC="AH17";
NET "dac_main_sync_n_o" LOC="AM17";
NET "dac_main_sclk_o" LOC="AN17";
NET "dac_main_data_o" LOC="AP17";
NET "pll_cs_n_o" LOC="AK18";
NET "pll_sck_o" LOC="AE16";
NET "pll_mosi_o" LOC="AH19";
NET "pll_miso_i" LOC="AJ19";
NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="AE18";
NET "pll_sync_n_o" LOC="AG18";
NET "uart_txd_o" LOC="AP16";
NET "uart_rxd_i" LOC="AJ17";
NET "clk_en_o" LOC="AD16";
NET "clk_sel_o" LOC="AK17";
NET "gtx0_3_clk_n_i" LOC="AK5";
NET "gtx0_3_clk_p_i" LOC="AK6";
NET "gtx0_3_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx0_3_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx16_19_clk_n_i" LOC="H5";
NET "gtx16_19_clk_p_i" LOC="H6";
NET "gtx16_19_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx16_19_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx12_15_clk_n_i" LOC="P5";
NET "gtx12_15_clk_p_i" LOC="P6";
NET "gtx12_15_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx12_15_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx_rxp_i[0]" LOC="AP5"; # gtx0
NET "gtx_rxn_i[0]" LOC="AP6";
NET "gtx_txp_o[0]" LOC="AP1";
NET "gtx_txn_o[0]" LOC="AP2";
NET "gtx_rxp_i[1]" LOC="AM5"; # gtx1
NET "gtx_rxn_i[1]" LOC="AM6";
NET "gtx_txp_o[1]" LOC="AN3";
NET "gtx_txn_o[1]" LOC="AN4";
NET "gtx_rxp_i[2]" LOC="AL3"; # gtx2
NET "gtx_rxn_i[2]" LOC="AL4";
NET "gtx_txp_o[2]" LOC="AM1";
NET "gtx_txn_o[2]" LOC="AM2";
NET "gtx_rxp_i[3]" LOC="J3"; # gtx15
NET "gtx_rxn_i[3]" LOC="J4";
NET "gtx_txp_o[3]" LOC="F1";
NET "gtx_txn_o[3]" LOC="F2";
NET "gtx_rxp_i[4]" LOC="G3"; # gtx16
NET "gtx_rxn_i[4]" LOC="G4";
NET "gtx_txp_o[4]" LOC="D1";
NET "gtx_txn_o[4]" LOC="D2";
NET "gtx_rxp_i[5]" LOC="E3"; # gtx17
NET "gtx_rxn_i[5]" LOC="E4";
NET "gtx_txp_o[5]" LOC="C3";
NET "gtx_txn_o[5]" LOC="C4";
NET "led_lact_o[0]" LOC="AG33";
NET "led_lact_o[1]" LOC="AF33";
NET "led_lact_o[2]" LOC="AC32";
NET "led_lact_o[3]" LOC="AC34"; #6
NET "led_lact_o[4]" LOC="AF34"; #0
NET "led_lact_o[5]" LOC="AE34"; #2
NET "mbl_sc0_b" LOC="AG32"; #74-36
NET "mbl_sc1_b" LOC="AC25"; #80-39
NET "mbl_sd0_b" LOC="AF31"; #76-37
NET "mbl_sd1_b" LOC="AG31"; #78-38
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/20
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/22
NET "fpga_clk_25mhz_n_i" TNM_NET = fpga_clk_25mhz_n_i;
TIMESPEC TS_fpga_clk_25mhz_n_i = PERIOD "fpga_clk_25mhz_n_i" 40 ns HIGH 50%;
NET "fpga_clk_25mhz_p_i" TNM_NET = fpga_clk_25mhz_p_i;
TIMESPEC TS_fpga_clk_25mhz_p_i = PERIOD "fpga_clk_25mhz_p_i" 40 ns HIGH 50%;
NET "fpga_clk_dmtd_n_i" TNM_NET = fpga_clk_dmtd_n_i;
TIMESPEC TS_fpga_clk_dmtd_n_i = PERIOD "fpga_clk_dmtd_n_i" 16 ns HIGH 50%;
NET "fpga_clk_dmtd_p_i" TNM_NET = fpga_clk_dmtd_p_i;
TIMESPEC TS_fpga_clk_dmtd_p_i = PERIOD "fpga_clk_dmtd_p_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_n_i" TNM_NET = fpga_clk_ref_n_i;
TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
NET "fpga_clk_sys_n_i" TNM_NET = fpga_clk_sys_n_i;
TIMESPEC TS_fpga_clk_sys_n_i = PERIOD "fpga_clk_sys_n_i" 16 ns HIGH 50%;
NET "fpga_clk_sys_p_i" TNM_NET = fpga_clk_sys_p_i;
TIMESPEC TS_fpga_clk_sys_p_i = PERIOD "fpga_clk_sys_p_i" 16 ns HIGH 50%;
NET "gen_phys[0].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_0__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[0].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[1].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[1].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_1__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[1].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[3].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[3].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_3__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[3].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[4].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[4].U_PHY/tx_out_clk_bufin;
TIMESPEC TS_gen_phys_4__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[4].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[0].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[0].U_PHY/tx_out_clk_bufin;
TIMESPEC TS_gen_phys_0__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[0].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[2].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[2].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_2__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[2].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[5].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[5].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_5__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[5].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[4].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_4__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
top/scb_18ports/scb_top_synthesis.vhd 0 → 100644
View file @ 0fbd4ec0
This diff is collapsed.
top/scb_6ports/Manifest.py
View file @ 0fbd4ec0
files = ["test_scb.vhd", "test_scb.ucf", "wb_cpu_bridge.vhd","wrsw_components_pkg.vhd"];
files = ["scb_top_synthesis.ucf", "scb_top_synthesis.vhd"];
modules = { "local" : [ "../../" ] };
modules = { "local" : [ "../../", "../bare_top" ] };
......
top/scb_6ports/scb_top_synthesis.ucf
View file @ 0fbd4ec0
......@@ -15,7 +15,6 @@ NET "fpga_clk_dmtd_n_i" LOC=M22;
#EBI BUS
#NET "cpu_clk_i" LOC="";
NET "cpu_cs_n_i" LOC="H34";
NET "cpu_wr_n_i" LOC="M25";
......@@ -48,7 +47,6 @@ NET "cpu_addr_i<1>" LOC="G31";
NET "cpu_addr_i<0>" LOC="D32";
#NET "cpu_addr_i<1>" LOC="H30";
#NET "cpu_addr_i<0>" LOC="J30";
NET "cpu_data_b<31>" LOC="T26";
NET "cpu_data_b<30>" LOC="R28";
NET "cpu_data_b<29>" LOC="R29";
......@@ -120,6 +118,7 @@ NET "gtx4_7_clk_p_i" LOC="AD6";
NET "gtx4_7_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx4_7_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx_rxp_i[0]" LOC="AP5";
NET "gtx_rxn_i[0]" LOC="AP6";
......@@ -157,23 +156,65 @@ NET "gtx_rxn_i[5]" LOC="AF6";
NET "gtx_txp_o[5]" LOC="AF1";
NET "gtx_txn_o[5]" LOC="AF2";
NET "gtx_sfp_tx_dis_o[0]" LOC="AD29";
NET "gtx_sfp_tx_dis_o[1]" LOC="AA29";
NET "gtx_sfp_tx_dis_o[2]" LOC="AC29";
NET "gtx_sfp_tx_dis_o[3]" LOC="AD31"; #GPIO30
NET "gtx_sfp_tx_dis_o[4]" LOC="AC28"; #GPIO33
NET "gtx_sfp_tx_dis_o[5]" LOC="AG32"; #GPIO36
NET "led_link_o[0]" LOC="AA26"; #GPIO14
NET "led_link_o[1]" LOC="AC30"; #GPIO13
NET "led_link_o[2]" LOC="AA31"; #GPIO11
NET "led_link_o[3]" LOC="AA34"; #GPIO9
NET "led_link_o[4]" LOC="AB33"; #GPIO7
NET "led_link_o[5]" LOC="AC33"; #GPIO5
NET "led_act_o[0]" LOC="AA28"; #GPIO15
NET "led_act_o[1]" LOC="AB30"; #GPIO12
NET "led_act_o[2]" LOC="AA33"; #GPIO10
NET "led_act_o[3]" LOC="AB32"; #GPIO8
NET "led_act_o[4]" LOC="AC34"; #GPIO6
NET "led_act_o[5]" LOC="AD34"; #GPIO4
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/20
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/22
NET "fpga_clk_25mhz_n_i" TNM_NET = fpga_clk_25mhz_n_i;
TIMESPEC TS_fpga_clk_25mhz_n_i = PERIOD "fpga_clk_25mhz_n_i" 40 ns HIGH 50%;
NET "fpga_clk_25mhz_p_i" TNM_NET = fpga_clk_25mhz_p_i;
TIMESPEC TS_fpga_clk_25mhz_p_i = PERIOD "fpga_clk_25mhz_p_i" 40 ns HIGH 50%;
NET "fpga_clk_dmtd_n_i" TNM_NET = fpga_clk_dmtd_n_i;
TIMESPEC TS_fpga_clk_dmtd_n_i = PERIOD "fpga_clk_dmtd_n_i" 16 ns HIGH 50%;
NET "fpga_clk_dmtd_p_i" TNM_NET = fpga_clk_dmtd_p_i;
TIMESPEC TS_fpga_clk_dmtd_p_i = PERIOD "fpga_clk_dmtd_p_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_n_i" TNM_NET = fpga_clk_ref_n_i;
TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
NET "fpga_clk_sys_n_i" TNM_NET = fpga_clk_sys_n_i;
TIMESPEC TS_fpga_clk_sys_n_i = PERIOD "fpga_clk_sys_n_i" 16 ns HIGH 50%;
NET "fpga_clk_sys_p_i" TNM_NET = fpga_clk_sys_p_i;
TIMESPEC TS_fpga_clk_sys_p_i = PERIOD "fpga_clk_sys_p_i" 16 ns HIGH 50%;
NET "gen_phys[0].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_0__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[0].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[1].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[1].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_1__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[1].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[3].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[3].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_3__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[3].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[4].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[4].U_PHY/tx_out_clk_bufin;
TIMESPEC TS_gen_phys_4__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[4].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[0].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[0].U_PHY/tx_out_clk_bufin;
TIMESPEC TS_gen_phys_0__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[0].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[2].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[2].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_2__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[2].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[5].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[5].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_5__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[5].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[4].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_4__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gtx0_3_clk_n_i" TNM_NET = gtx0_3_clk_n_i;
TIMESPEC TS_gtx0_3_clk_n_i = PERIOD "gtx0_3_clk_n_i" 8 ns HIGH 50%;
NET "gtx0_3_clk_p_i" TNM_NET = gtx0_3_clk_p_i;
TIMESPEC TS_gtx0_3_clk_p_i = PERIOD "gtx0_3_clk_p_i" 8 ns HIGH 50%;
NET "gtx4_7_clk_p_i" TNM_NET = gtx4_7_clk_p_i;
TIMESPEC TS_gtx4_7_clk_p_i = PERIOD "gtx4_7_clk_p_i" 8 ns HIGH 50%;
NET "gtx4_7_clk_n_i" TNM_NET = gtx4_7_clk_n_i;
TIMESPEC TS_gtx4_7_clk_n_i = PERIOD "gtx4_7_clk_n_i" 8 ns HIGH 50%;
top/scb_6ports/scb_top_synthesis.vhd 0 → 100644
View file @ 0fbd4ec0
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