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White Rabbit Switch - Gateware
Commit 0fea77b8 authored by Maciej Lipinski's avatar Maciej Lipinski
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Merge branch 'hm_proposed_master' into 'proposed_master' 

Hm proposed master

See merge request !1
parents 9a26b13e 4d68cb12
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Showing with 132 additions and 38 deletions
modules/wrsw_hwiu/gw_ver_pkg.vhd
View file @ 0fea77b8
......@@ -2,8 +2,8 @@ library ieee;
use ieee.std_logic_1164.all;
--generated automatically by gen_ver.py script--
package hwver_pkg is
constant c_build_date : std_logic_vector(31 downto 0) := x"06041400";
constant c_switch_hdl_ver : std_logic_vector(31 downto 0) := x"04e89257";
constant c_build_date : std_logic_vector(31 downto 0) := x"0e051400";
constant c_switch_hdl_ver : std_logic_vector(31 downto 0) := x"092bce2d";
constant c_gencores_ver : std_logic_vector(31 downto 0) := x"0dcc7cc3";
constant c_wrcores_ver : std_logic_vector(31 downto 0) := x"08299d65";
end package;
syn/scb_18ports/test_scb.xise
View file @ 0fea77b8
......@@ -1251,7 +1251,7 @@
<property xil_pn:name="Output File Name" xil_pn:value="scb_top_synthesis" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Outputs Only" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="ff1156" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -1363,7 +1363,7 @@
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
......
top/bare_top/scb_top_bare.vhd
View file @ 0fea77b8
......@@ -83,8 +83,8 @@ entity scb_top_bare is
-- for re-phasing the 10 MHz input as well as clocking the
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic; -- going to CLK2 SMC on the front pannel, by
clk_aux_n_o : out std_logic; -- default it's 10MHz, but is configurable
......@@ -145,6 +145,7 @@ entity scb_top_bare is
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_present_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
-- LJD AD9516
ljd_pll_mosi_o : out std_logic;
......@@ -466,6 +467,7 @@ architecture rtl of scb_top_bare is
signal nic_rtu_rsp : t_rtu_response;
signal nic_rtu_ack : std_logic;
signal ljd_present : std_logic;
signal ljd_detected : std_logic;
signal dac_main_sync_n : std_logic;
signal dac_main_sclk : std_logic;
......@@ -1332,12 +1334,14 @@ begin
-------------------------------------------------------------------------------
-- WRS Low jitter daughterboard
-------------------------------------------------------------------------------
ljd_present <= '1' when ((ljd_detected='1') and (ljd_osc_freq_i/="111")) else '0';
ljd_detected_o <= ljd_detected;
ljd_present_o <= ljd_present;
-- Redirect DAC output if external board detetected
dac_redirection : process (ljd_detected, dac_main_sync_n, dac_main_sclk, dac_main_data)
dac_redirection : process (ljd_present, dac_main_sync_n, dac_main_sclk, dac_main_data)
begin
if (ljd_detected = '0') then
if (ljd_present = '0') then
dac_main_sync_n_o <= dac_main_sync_n;
dac_main_sclk_o <= dac_main_sclk;
dac_main_data_o <= dac_main_data;
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 0fea77b8
......@@ -370,6 +370,7 @@ package wrsw_top_pkg is
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_present_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ 0fea77b8
This diff is collapsed.
top/scb_18ports/scb_top_synthesis.vhd
View file @ 0fea77b8
......@@ -331,6 +331,7 @@ architecture Behavioral of scb_top_synthesis is
signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
signal clk_ext_mul_locked : std_logic;
signal ljd_detected : std_logic := '0';
signal ljd_present : std_logic := '0';
signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic;
signal ljd_clk_62mhz, ljd_clk_62mhz_bufr : std_logic;
......@@ -380,6 +381,7 @@ architecture Behavioral of scb_top_synthesis is
ljd_clk1_en : out std_logic;
ljd_clk2_en : out std_logic;
ljd_detected_o : out std_logic;
ljd_present_o : out std_logic;
ljd_osc_freq_i : in std_logic_vector (2 downto 0);
ljd_pll_mosi_o : out std_logic;
ljd_pll_miso_i : in std_logic;
......@@ -625,8 +627,8 @@ begin
O => clk_10mhz,
I0 => clk_ext,
I1 => ext_clk_10MHz_bufr,
S1 => ljd_detected,
S0 => NOT ljd_detected);
S1 => ljd_present,
S0 => NOT ljd_present);
U_Buf_CLK_DMTD : IBUFGDS
generic map (
......@@ -896,6 +898,7 @@ begin
ljd_clk1_en => ljd_clk1_en,
ljd_clk2_en => ljd_clk2_en,
ljd_detected_o => ljd_detected,
ljd_present_o => ljd_present,
ljd_osc_freq_i => ljd_osc_freq_i,
ljd_pll_mosi_o => ljd_pll_mosi_o,
ljd_pll_miso_i => ljd_pll_miso_i,
......
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