swcore/mpm_async_grow_fifo: added almost full output, throttle traffic a bit in advance

15aac01c · Tomasz Wlostowski · 2a36321b · 15aac01c · 15aac01c
Commit 15aac01c authored Feb 19, 2014 by Tomasz Wlostowski
Hide whitespace changes
Inline Side-by-side

Showing with 25 additions and 11 deletions

mpm_async_fifo_ctrl.vhd modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd +24 -8

mpm_async_grow_fifo.vhd modules/wrsw_swcore/mpm/mpm_async_grow_fifo.vhd +1 -3

No files found.
--- a/modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_async_fifo_ctrl.vhd
@@ -92,13 +92,14 @@ architecture rtl of mpm_async_fifo_ctrl is

  type t_counter_block is record
    bin, bin_next, gray, gray_next : t_counter;
-    bin_x, gray_x, gray_xm                       : t_counter;
+    bin_x, gray_x, gray_xm         : t_counter;
  end record;


-  signal rcb, wcb            : t_counter_block;
-  signal full_int, empty_int : std_logic;
-  signal going_full          : std_logic;
+  signal rcb, wcb                         : t_counter_block;
+  signal wr_count                         : t_counter;
+  signal full_int, empty_int, almost_full : std_logic;
+  signal going_full                       : std_logic;
  
 begin  -- rtl

@@ -138,16 +139,16 @@ begin  -- rtl
  begin
    if rising_edge(clk_wr_i) then
      rcb.gray_xm <= rcb.gray;
-      rcb.gray_x <= rcb.gray_xm;
+      rcb.gray_x  <= rcb.gray_xm;
    end if;
  end process;

- 
+
  p_sync_write_ptr : process(clk_rd_i)
  begin
    if rising_edge(clk_rd_i) then
      wcb.gray_xm <= wcb.gray;
-      wcb.gray_x <= wcb.gray_xm;
+      wcb.gray_x  <= wcb.gray_xm;
    end if;
  end process;

@@ -181,6 +182,21 @@ begin  -- rtl
    end if;
  end process;

+  p_gen_almost_full : process(clk_wr_i, rst_n_a_i)
+  begin
+    if rst_n_a_i = '0' then
+      wr_count    <= (others => '0');
+      almost_full <= '0';
+    elsif rising_edge(clk_wr_i) then
+      wr_count <= wcb.bin_x - rcb.bin;
+      if(wr_count >= g_size - 2) then
+        almost_full <= '1';
+      else
+        almost_full <= '0';
+      end if;
+    end if;
+  end process;
+
  p_register_full : process(clk_wr_i, rst_n_a_i)
  begin
    if rst_n_a_i = '0' then
@@ -192,7 +208,7 @@ begin  -- rtl

  full_o       <= full_int;
  empty_o      <= empty_int;
-  going_full_o <= going_full;
+  going_full_o <= almost_full;

  wr_addr_o <= std_logic_vector(wcb.bin(wcb.bin'left-1 downto 0));
  rd_addr_o <= std_logic_vector(rcb.bin(rcb.bin'left-1 downto 0));

--- a/modules/wrsw_swcore/mpm/mpm_async_grow_fifo.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_async_grow_fifo.vhd
@@ -212,15 +212,13 @@ begin  -- rtl
  p_output_reg : process(clk_rd_i)
  begin
  	if rising_edge(clk_rd_i) then
-- 	if rd_i = '1' then
 	  q_o    <= q_int;
 	  side_o <= side_comb;
-- 	end if;
    end if;
  end process;

  -- full flag is only active when there's no space left in the highest memory
  -- cell
-  full_o <= full_int and (wr_sreg(wr_sreg'left) or (wr_sreg(wr_sreg'left - 1) and we_i));
+  full_o <= full_int;
  
 end rtl;