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White Rabbit Switch - Gateware
Commit 16001e42 authored by Maciej Lipinski's avatar Maciej Lipinski
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[swcore/out_blk] added hwdu_dbg of FMSs states

parent 86f6256f
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Showing with 44 additions and 7 deletions
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @ 16001e42
......@@ -501,6 +501,7 @@ package swc_swcore_pkg is
g_mpm_partial_select_width : integer ;
g_mpm_fetch_next_pg_in_advance : boolean := false;
g_mmu_resource_num_width : integer;
g_hwdu_output_block_width : integer :=8;
g_wb_data_width : integer ;
g_wb_addr_width : integer ;
g_wb_sel_width : integer ;
......@@ -532,6 +533,7 @@ package swc_swcore_pkg is
ots_output_drop_at_rx_hp_i : in std_logic;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
dbg_hwdu_o : out std_logic_vector(g_hwdu_output_block_width -1 downto 0);
tap_out_o : out std_logic_vector(15 downto 0)
);
......
modules/wrsw_swcore/xswc_core.vhd
View file @ 16001e42
......@@ -153,6 +153,7 @@ architecture rtl of xswc_core is
----------------------------------------------
constant c_hwdu_input_block_width : integer := 16;
constant c_hwdu_mmu_width : integer := 10*3;
constant c_hwdu_output_block_width : integer := 8;
----------------------------------------------------------------------------------------------------
-- signals connecting >>Input Block<< with >>Memory Management Unit<<
......@@ -352,8 +353,10 @@ architecture rtl of xswc_core is
signal mmu2ib_set_usecnt_succeeded : std_logic_vector(g_num_ports -1 downto 0);
type t_hwdu_input_block_array is array(0 to g_num_ports-1) of std_logic_vector(c_hwdu_input_block_width-1 downto 0);
type t_hwdu_output_block_array is array(0 to g_num_ports-1) of std_logic_vector(c_hwdu_output_block_width-1 downto 0);
signal hwdu_input_block : t_hwdu_input_block_array;
signal hwdu_output_block : t_hwdu_output_block_array;
signal hwdu_mmu : std_logic_vector(c_hwdu_mmu_width -1 downto 0);
signal dbg_pckstart_pageaddr : std_logic_vector(g_num_ports*c_mpm_page_addr_width - 1 downto 0);
......@@ -559,7 +562,7 @@ architecture rtl of xswc_core is
src_i => src_i(i),
src_o => src_o(i),
dbg_hwdu_o => hwdu_output_block(i),
tap_out_o => tap_ob(i)
);
......@@ -798,8 +801,12 @@ architecture rtl of xswc_core is
dbg_o(31 downto 0) <= "00" & hwdu_mmu;
hwdu_gen: for i in 0 to (g_num_ports-1) generate
dbg_o((i+1)*c_hwdu_input_block_width+32-1 downto i*c_hwdu_input_block_width+32) <= hwdu_input_block(i);
hwdu_gen: for i in 0 to (g_num_ports-1) generate --19 ports for 18-port switch
dbg_o((i+1)*c_hwdu_input_block_width+32-1 downto
i*c_hwdu_input_block_width+32) <= hwdu_input_block(i);
dbg_o((i+1)*c_hwdu_output_block_width+(g_num_ports*c_hwdu_input_block_width)+32-1 downto
i*c_hwdu_output_block_width+(g_num_ports*c_hwdu_input_block_width)+32) <= hwdu_output_block(i);
end generate hwdu_gen;
end rtl;
modules/wrsw_swcore/xswc_output_block_new.vhd
View file @ 16001e42
......@@ -76,6 +76,7 @@ entity xswc_output_block_new is
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_wb_sel_width : integer;
g_hwdu_output_block_width : integer := 8;
g_wb_ob_ignore_ack : boolean := true;
g_drop_outqueue_head_on_full : boolean := true
);
......@@ -129,6 +130,10 @@ entity xswc_output_block_new is
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
-------------------------------------------------------------------------------
-- debugging
-------------------------------------------------------------------------------
dbg_hwdu_o : out std_logic_vector(g_hwdu_output_block_width -1 downto 0);
tap_out_o : out std_logic_vector(15 downto 0)
);
end xswc_output_block_new;
......@@ -296,6 +301,9 @@ architecture behavoural of xswc_output_block_new is
signal cyc_d0 : std_logic;
signal drop_at_retry : std_logic; --
signal send_FSM : std_logic_vector(3 downto 0);
signal prep_FSM : std_logic_vector(3 downto 0);
constant tx_interframe_gap : unsigned(3 downto 0) := x"1";-- x"2"; !!!! changed it on 8-Nov-2013, brave thing to change something that almost works
-- if TRUE, any time a retry request is received from EP (most probably PCS), the request
......@@ -881,7 +889,9 @@ begin -- behavoural
--===========================================================================================
when others =>
--===========================================================================================
s_send_pck <= S_IDLE;
s_send_pck <= S_IDLE;
src_out_int.cyc <= '0';
src_out_int.stb <= '0';
end case;
end if;
end if;
......@@ -1002,4 +1012,21 @@ begin -- behavoural
ppfm_free_o <= ppfm_free;
ppfm_free_pgaddr_o <= ppfm_free_pgaddr;
send_FSM <= x"0" when (s_send_pck = S_IDLE) else
x"1" when (s_send_pck = S_DATA) else
x"2" when (s_send_pck = S_FLUSH_STALL) else
x"3" when (s_send_pck = S_FINISH_CYCLE) else
x"4" when (s_send_pck = S_EOF) else
x"5" when (s_send_pck = S_RETRY) else
x"6" when (s_send_pck = S_WAIT_FREE_PCK) else
x"7" ;
prep_FSM <= x"5" when (s_prep_to_send = S_IDLE) else
x"1" when (s_prep_to_send = S_NEWPCK_PAGE_READY) else
x"2" when (s_prep_to_send = S_NEWPCK_PAGE_SET_IN_ADVANCE) else
x"3" when (s_prep_to_send = S_NEWPCK_PAGE_USED) else
x"4" when (s_prep_to_send = S_RETRY_PREPARE) else
x"0" when (s_prep_to_send = S_RETRY_READY) else
x"6" ;
dbg_hwdu_o(7 downto 0)<= send_FSM & prep_FSM;
end behavoural;
top/bare_top/wrsw_components_pkg.vhd
View file @ 16001e42
......@@ -336,7 +336,7 @@ package wrsw_components_pkg is
clk_i : in std_logic;
dbg_regs_i : in std_logic_vector(g_nregs*g_rwidth-1 downto 0);
dbg_chps_id_o : out std_logic_vector(7 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 16001e42
......@@ -397,7 +397,8 @@ package wrsw_top_pkg is
clk_i : in std_logic;
dbg_regs_i : in std_logic_vector(g_nregs*g_rwidth-1 downto 0);
dbg_chps_id_o : out std_logic_vector(7 downto 0);
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
......
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