WRS-FL: Updated periph_id reservation for WRS-FL

It turned out that WRS-FL uses periph_id 0x7 for v1.0 and 0x6 for v1.5. Updated accordingly.

WRS-FL: Updated periph_id reservation for WRS-FL
It turned out that WRS-FL uses periph_id 0x7 for v1.0 and 0x6 for v1.5. Updated accordingly.
163c4ffa · Maciej Lipinski · 643c39d1 · 163c4ffa
Commit 163c4ffa authored Dec 09, 2023 by Maciej Lipinski
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scb_top_bare.vhd top/bare_top/scb_top_bare.vhd +5 -3

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--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -220,7 +220,7 @@ end scb_top_bare;

 architecture rtl of scb_top_bare is

-  constant c_GW_VERSION    : std_logic_vector(31 downto 0) := x"23_12_05_00"; --DD_MM_YY_VV
+  constant c_GW_VERSION    : std_logic_vector(31 downto 0) := x"23_12_09_00"; --DD_MM_YY_VV
  constant c_NUM_WB_SLAVES : integer := 15;
  constant c_NUM_PORTS     : integer := g_num_ports;
  constant c_MAX_PORTS     : integer := 18;
@@ -1370,8 +1370,9 @@ begin
    --------------------------------------------------------------------------
     -- SyncTech WRS-FL with low-jitter capability integrated into main board
     -- Versions supported: WRS-FL v1.0 and v1.5
+     -- lj_periph_id_i: 0x7 for v1.0, 0x6 for v1.5
    --------------------------------------------------------------------------
-    elsif (lj_osc_freq_i = "111"  and lj_periph_id_i = "111" ) then
+    elsif (lj_osc_freq_i = "111"  and (lj_periph_id_i = "111"  or lj_periph_id_i = "110")) then
      dac_main_sync_n_o     <= dac_main_sync_n;
      dac_main_sclk_o       <= dac_main_sclk;
      dac_main_data_o       <= dac_main_data;
@@ -1380,10 +1381,11 @@ begin
      lj_dac_main_data_o    <= '0';
      lj_ext_gm_clk_diff_o  <= '0';
      
-    elsif (lj_osc_freq_i = "111"  and lj_periph_id_i = "110") then 
+    elsif (lj_osc_freq_i = "111"  and lj_periph_id_i = "101") then 
    --------------------------------------------------------------------------
     -- Safran WRS-LJ with low-jitter capability integrated into main board
     -- Versions supported: WRS-LJ v1.2
+     -- lj_periph_id_i: 0x5
    --------------------------------------------------------------------------
      dac_main_sync_n_o     <= dac_main_sync_n;
      dac_main_sclk_o       <= dac_main_sclk;