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White Rabbit Switch - Gateware
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White Rabbit Switch - Gateware
Commits
1a8c42fa
Commit
1a8c42fa
authored
Aug 12, 2019
by
Grzegorz Daniluk
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rename ext_board_check to wrsw_ext_board_check
parent
5e7d55d6
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4 changed files
with
10 additions
and
10 deletions
+10
-10
Manifest.py
modules/wrsw_ext_board/Manifest.py
+1
-1
wrsw_ext_board_check.vhd
modules/wrsw_ext_board/wrsw_ext_board_check.vhd
+5
-5
scb_top_synthesis.vhd
top/scb_18ports/scb_top_synthesis.vhd
+2
-2
scb_top_synthesis.vhd
top/scb_8ports/scb_top_synthesis.vhd
+2
-2
No files found.
modules/wrsw_ext_board/Manifest.py
View file @
1a8c42fa
files
=
[
"ext_board_check.vhd"
];
files
=
[
"
wrsw_
ext_board_check.vhd"
];
modules/wrsw_ext_board/ext_board_check.vhd
→
modules/wrsw_ext_board/
wrsw_
ext_board_check.vhd
View file @
1a8c42fa
-------------------------------------------------------------------------------
-- Title : ext_board_check
-- Title :
wrsw_
ext_board_check
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : ext_board_check.vhd
-- File :
wrsw_
ext_board_check.vhd
-- Author : Mattia Rzzi
-- Company : CERN BE-CO-HT
-- Platform : FPGA-generic
...
...
@@ -45,7 +45,7 @@ use work.wrsw_top_pkg.all;
library
UNISIM
;
use
UNISIM
.
vcomponents
.
all
;
entity
ext_board_check
is
entity
wrsw_
ext_board_check
is
generic
(
g_pattern
:
std_logic_vector
(
63
downto
0
)
:
=
x"CAFED00DCAFED00D"
;
g_clk_divider
:
integer
:
=
16
);
...
...
@@ -56,9 +56,9 @@ entity ext_board_check is
loopback_o
:
out
std_logic
;
board_detected_o
:
out
std_logic
);
end
ext_board_check
;
end
wrsw_
ext_board_check
;
architecture
Behavioral
of
ext_board_check
is
architecture
Behavioral
of
wrsw_
ext_board_check
is
signal
clk_divider
:
integer
range
0
to
g_clk_divider
-1
;
signal
clk_en
:
std_logic
;
...
...
top/scb_18ports/scb_top_synthesis.vhd
View file @
1a8c42fa
...
...
@@ -244,7 +244,7 @@ architecture Behavioral of scb_top_synthesis is
locked_o
:
out
std_logic
);
end
component
;
component
ext_board_check
is
component
wrsw_
ext_board_check
is
generic
(
g_pattern
:
std_logic_vector
(
63
downto
0
)
:
=
x"CAFED00DCAFED00D"
;
g_clk_divider
:
integer
:
=
16
);
...
...
@@ -674,7 +674,7 @@ begin
clk_ext_mul_locked
<=
ext_pll_100_locked
and
ext_pll_62_locked
;
-- Detect the external board (WRS Low jitter daughterboard)
ext_board_checker_inst
:
ext_board_check
ext_board_checker_inst
:
wrsw_
ext_board_check
generic
map
(
g_clk_divider
=>
16
,
g_pattern
=>
x"CAFED00DCAFED00D"
)
...
...
top/scb_8ports/scb_top_synthesis.vhd
View file @
1a8c42fa
...
...
@@ -246,7 +246,7 @@ architecture Behavioral of scb_top_synthesis is
locked_o
:
out
std_logic
);
end
component
;
component
ext_board_check
is
component
wrsw_
ext_board_check
is
generic
(
g_pattern
:
std_logic_vector
(
63
downto
0
)
:
=
x"CAFED00DCAFED00D"
;
g_clk_divider
:
integer
:
=
16
);
...
...
@@ -624,7 +624,7 @@ begin
CLKIN
=>
clk_25mhz
);
-- Detect the external board (WRS Low jitter daughterboard)
ext_board_checker_inst
:
ext_board_check
ext_board_checker_inst
:
wrsw_
ext_board_check
generic
map
(
g_clk_divider
=>
16
,
g_pattern
=>
x"CAFED00DCAFED00D"
)
...
...
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