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White Rabbit Switch - Gateware
Commit 1fa11847 authored by Maciej Lipinski's avatar Maciej Lipinski
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[testbench/alloc] update to verify new alloc

parent c736c805
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Showing with 7 additions and 5 deletions
testbench/swcore/allocator/Manifest.py
View file @ 1fa11847
target = "xilinx" # "altera" #
action = "simulation"
#fetchto = "../../ip_cores"
fetchto = "../../../ip_cores"
files = [
"main.sv"
......@@ -11,8 +11,9 @@ vlog_opt="+incdir+../../ip_cores/wr-cores/sim +incdir+../../ip_cores/wr-cores/si
modules = {"local":
[
"../../../ip_cores/wr-cores",
"../../../ip_cores/wr-cores/ip_cores/general-cores/modules/genrams/",
"../../../modules/wrsw_swcore",
"../../../",
#"../../../ip_cores/wr-cores",
#"../../../ip_cores/wr-cores/ip_cores/general-cores/modules/genrams/",
#"../../../modules/wrsw_swcore"
],
}
testbench/swcore/allocator/run.do
View file @ 1fa11847
make -f Makefile
vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim multiport.sv
# vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim multiport.sv
vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim main.sv
vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
......
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