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White Rabbit Switch - Gateware
Commit 21b75b20 authored by Maciej Lipinski's avatar Maciej Lipinski
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swcore[v2->v3 port]: working with new genrams, still on altera

parent 02e559b4
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Showing with 106 additions and 105 deletions
modules/wrsw_swcore/Manifest.py
View file @ 21b75b20
......@@ -6,7 +6,8 @@
# "swc_pipelined_mux.vhd",
# "swc_async_multiport_mem.vhd"]
files = ["swc_swcore_pkg.vhd",
files = [
"swc_swcore_pkg.vhd",
"swc_block_alloc.vhd",
"swc_core.vhd",
"swc_input_block.vhd",
......
modules/wrsw_swcore/swc_multiport_linked_list.vhd
View file @ 21b75b20
......@@ -149,7 +149,7 @@ architecture syn of swc_multiport_linked_list is
signal free_pck_read_done : std_logic_vector(c_swc_num_ports-1 downto 0);
signal ram_zeros : std_logic_vector( c_swc_page_addr_width - 1 downto 0);
signal ram_ones : std_logic_vector((c_swc_page_addr_width+7)/8 - 1 downto 0);
signal ram_ones : std_logic_vector((c_swc_page_addr_width)/8 - 1 downto 0);
begin -- syn
......@@ -157,43 +157,43 @@ begin -- syn
ram_zeros <=(others => '0');
ram_ones <=(others => '1');
PAGE_INDEX_LINKED_LIST : generic_ssram_dualport_singleclock
-- PAGE_INDEX_LINKED_LIST : generic_ssram_dualport_singleclock
-- generic map (
-- g_width => c_swc_page_addr_width,
-- g_addr_bits => c_swc_page_addr_width,
-- g_size => c_swc_packet_mem_num_pages --c_swc_packet_mem_size / c_swc_packet_mem_multiply
-- )
-- port map (
-- clk_i => clk_i,
-- rd_addr_i => ll_rd_addr,
-- wr_addr_i => ll_wr_addr,
-- data_i => ll_wr_data,
-- wr_en_i => ll_write_enable ,
-- q_o => ll_read_data);
PAGE_INDEX_LINKED_LIST : generic_dpram
generic map (
g_width => c_swc_page_addr_width,
g_addr_bits => c_swc_page_addr_width,
g_size => c_swc_packet_mem_num_pages --c_swc_packet_mem_size / c_swc_packet_mem_multiply
)
g_data_width => c_swc_page_addr_width,
g_size => c_swc_packet_mem_num_pages
)
port map (
clk_i => clk_i,
rd_addr_i => ll_rd_addr,
wr_addr_i => ll_wr_addr,
data_i => ll_wr_data,
wr_en_i => ll_write_enable ,
q_o => ll_read_data);
-- PAGE_INDEX_LINKED_LIST : generic_dpram
-- generic map (
-- g_data_width => c_swc_page_addr_width,
-- g_size => c_swc_packet_mem_num_pages
-- )
-- port map (
-- -- Port A -- writing
-- clka_i => clk_i,
-- bwea_i => ram_ones,
-- wea_i => ll_write_enable,
-- aa_i => ll_wr_addr,
-- da_i => ll_wr_data,
-- qa_o => open,
--
-- -- Port B -- reading
-- clkb_i => clk_i,
-- bweb_i => ram_ones,
-- web_i => '0',
-- ab_i => ll_rd_addr,
-- db_i => ram_zeros,
-- qb_o => ll_read_data
-- );
-- Port A -- writing
clka_i => clk_i,
bwea_i => ram_ones,
wea_i => ll_write_enable,
aa_i => ll_wr_addr,
da_i => ll_wr_data,
qa_o => open,
-- Port B -- reading
clkb_i => clk_i,
bweb_i => ram_ones,
web_i => '0',
ab_i => ll_rd_addr,
db_i => ram_zeros,
qb_o => ll_read_data
);
gen_write_request_vec : for i in 0 to c_swc_num_ports - 1 generate
......
modules/wrsw_swcore/swc_output_block.vhd
View file @ 21b75b20
......@@ -286,43 +286,43 @@ begin -- behavoural
);
end generate prio_ctrl;
PRIO_QUEUE : generic_ssram_dualport_singleclock
-- PRIO_QUEUE : generic_ssram_dualport_singleclock
-- generic map (
-- g_width => c_swc_page_addr_width + c_swc_max_pck_size_width,
-- g_addr_bits => c_swc_output_prio_num_width + c_swc_output_fifo_addr_width,
-- g_size => (c_swc_output_prio_num * c_swc_output_fifo_size)
-- )
-- port map (
-- clk_i => clk_i,
-- rd_addr_i => rd_addr,
-- wr_addr_i => wr_addr,
-- data_i => wr_data,
-- wr_en_i => wr_en,
-- q_o => rd_data
-- );
PRIO_QUEUE : generic_dpram
generic map (
g_width => c_swc_page_addr_width + c_swc_max_pck_size_width,
g_addr_bits => c_swc_output_prio_num_width + c_swc_output_fifo_addr_width,
g_data_width => c_swc_page_addr_width + c_swc_max_pck_size_width,
g_size => (c_swc_output_prio_num * c_swc_output_fifo_size)
)
port map (
clk_i => clk_i,
rd_addr_i => rd_addr,
wr_addr_i => wr_addr,
data_i => wr_data,
wr_en_i => wr_en,
q_o => rd_data
);
-- PRIO_QUEUE : generic_dpram
-- generic map (
-- g_data_width => c_swc_page_addr_width + c_swc_max_pck_size_width,
-- g_size => (c_swc_output_prio_num * c_swc_output_fifo_size)
-- )
-- port map (
-- -- Port A -- writing
-- clka_i => clk_i,
-- bwea_i => ram_ones,
-- wea_i => wr_en,
-- aa_i => wr_addr,
-- da_i => wr_data,
-- qa_o => open,
--
-- -- Port B -- reading
-- clkb_i => clk_i,
-- bweb_i => ram_ones,
-- web_i => '0',
-- ab_i => rd_addr,
-- db_i => ram_zeros,
-- qb_o => rd_data
-- );
-- Port A -- writing
clka_i => clk_i,
bwea_i => ram_ones,
wea_i => wr_en,
aa_i => wr_addr,
da_i => wr_data,
qa_o => open,
-- Port B -- reading
clkb_i => clk_i,
bweb_i => ram_ones,
web_i => '0',
ab_i => rd_addr,
db_i => ram_zeros,
qb_o => rd_data
);
rd_valid : process(clk_i, rst_n_i)
begin
......
modules/wrsw_swcore/swc_packet_mem.vhd
View file @ 21b75b20
......@@ -434,42 +434,42 @@ begin -- rtl
end process;
-- The most important part, the shared memory
FUCKING_BIG_MEMORY : generic_ssram_dualport_singleclock
-- FUCKING_BIG_MEMORY : generic_ssram_dualport_singleclock
-- generic map (
-- g_width => c_swc_packet_mem_multiply * c_swc_pump_width,
-- g_addr_bits => c_swc_packet_mem_addr_width,
-- g_size => c_swc_packet_mem_size / c_swc_packet_mem_multiply)
-- port map (
-- clk_i => clk_i,
-- rd_addr_i => ram_rd_addr_muxed,
-- wr_addr_i => ram_wr_addr_muxed,
-- data_i => ram_wr_data_muxed,
-- wr_en_i => ram_we_muxed,
-- q_o => ram_rd_data);
FUCKING_BIG_MEMORY : generic_dpram
generic map (
g_width => c_swc_packet_mem_multiply * c_swc_pump_width,
g_addr_bits => c_swc_packet_mem_addr_width,
g_size => c_swc_packet_mem_size / c_swc_packet_mem_multiply)
g_data_width => c_swc_packet_mem_multiply * c_swc_pump_width,
g_size => (c_swc_packet_mem_size / c_swc_packet_mem_multiply)
)
port map (
clk_i => clk_i,
rd_addr_i => ram_rd_addr_muxed,
wr_addr_i => ram_wr_addr_muxed,
data_i => ram_wr_data_muxed,
wr_en_i => ram_we_muxed,
q_o => ram_rd_data);
-- FUCKING_BIG_MEMORY : generic_dpram
-- generic map (
-- g_data_width => c_swc_packet_mem_multiply * c_swc_pump_width,
-- g_size => (c_swc_packet_mem_size / c_swc_packet_mem_multiply)
-- )
-- port map (
-- -- Port A -- writing
-- clka_i => clk_i,
-- bwea_i => ram_ones,
-- wea_i => ram_we_muxed,
-- aa_i => ram_wr_addr_muxed,
-- da_i => ram_wr_data_muxed,
-- qa_o => open,
--
-- -- Port B -- reading
-- clkb_i => clk_i,
-- bweb_i => ram_ones,
-- web_i => '0',
-- ab_i => ram_rd_addr_muxed,
-- db_i => ram_zeros,
-- qb_o => ram_rd_data
-- );
-- Port A -- writing
clka_i => clk_i,
bwea_i => ram_ones,
wea_i => ram_we_muxed,
aa_i => ram_wr_addr_muxed,
da_i => ram_wr_data_muxed,
qa_o => open,
-- Port B -- reading
clkb_i => clk_i,
bweb_i => ram_ones,
web_i => '0',
ab_i => ram_rd_addr_muxed,
db_i => ram_zeros,
qb_o => ram_rd_data
);
-- read pump: it reads c_swc_packet_mem_multiply words (ctrl + data) from FB SRAM and makes it
......
testbench/swcore/Manifest.py
View file @ 21b75b20
......@@ -13,7 +13,6 @@ modules = {"local":
"../../platform/genrams/altera",
#"../../ip_cores/general-cores/modules/genrams/",
"../../modules/wrsw_swcore",
#"../../ip_cores/wr-cores/modules/wr_endpoint", # for wr_fabric_pkg
],
#"git" :
#[
......
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