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White Rabbit Switch - Gateware
Commit 22382623 authored by Maciej Lipinski's avatar Maciej Lipinski
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TATSU: added new module: Time-Aware Traffic Shaper - it enables to define… 

TATSU: added new module: Time-Aware Traffic Shaper - it enables to define time-windows in which only configured output queues allowed (the rest is blocked). It uses the PAUSE mechanism in SWcore
parent aff2aa68
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Manifest.py
View file @ 22382623
......@@ -5,6 +5,7 @@ modules = { "local" : [
"modules/wrsw_swcore",
"modules/wrsw_rtu",
"modules/wrsw_tru",
"modules/wrsw_tatsu",
"platform/virtex6/chipscope",
"platform/xilinx"],
"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git" ]
......
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
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......@@ -61,6 +61,11 @@ entity wrsw_rt_subsystem is
sel_clk_sys_o : out std_logic; -- system clock selection: 0 = startup
-- clock, 1 = PLL clock
-- WR timebase
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic;
-- AD9516 signals
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
......@@ -327,10 +332,9 @@ begin -- rtl
pps_csync_o => pps_csync_o,
pps_out_o => pps_ext_o,
pps_valid_o => pps_valid_o,
tm_utc_o => open,
tm_cycles_o => open,
tm_time_valid_o => open);
tm_utc_o => tm_utc_o,
tm_cycles_o => tm_cycles_o,
tm_time_valid_o => tm_time_valid_o);
cpu_irq_vec(0) <= cnx_master_in(2).int;
cpu_irq_vec(31 downto 1) <= (others => '0');
......
modules/wrsw_tatsu/Manifest.py 0 → 100644
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files = [
"xwrsw_tatsu.vhd",
"wrsw_tatsu_pkg.vhd",
"tatsu_wbgen2_pkg.vhd",
"tatsu_wishbone_controller.vhd",
"../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd",
"../../ip_cores/general-cores/modules/common/gencores_pkg.vhd",
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd",
"../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd",
]
\ No newline at end of file
modules/wrsw_tatsu/tatsu_wbgen2_pkg.vhd 0 → 100644
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---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR switch Time Aware Traffic Shaper controller
---------------------------------------------------------------------------------------
-- File : tatsu_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from tatsu_wishbone_controller.wb
-- Created : Sun Mar 3 20:53:36 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tatsu_wishbone_controller.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tatsu_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_tatsu_in_registers is record
tcr_min_rpt_i : std_logic_vector(7 downto 0);
tcr_started_i : std_logic;
tcr_delayed_i : std_logic;
tcr_stg_ok_i : std_logic;
tcr_stg_err_i : std_logic;
tcr_stg_err_tai_i : std_logic;
tcr_stg_err_cyc_i : std_logic;
tcr_stg_err_rpt_i : std_logic;
tcr_stg_err_snc_i : std_logic;
end record;
constant c_tatsu_in_registers_init_value: t_tatsu_in_registers := (
tcr_min_rpt_i => (others => '0'),
tcr_started_i => '0',
tcr_delayed_i => '0',
tcr_stg_ok_i => '0',
tcr_stg_err_i => '0',
tcr_stg_err_tai_i => '0',
tcr_stg_err_cyc_i => '0',
tcr_stg_err_rpt_i => '0',
tcr_stg_err_snc_i => '0'
);
-- Output registers (WB slave -> user design)
type t_tatsu_out_registers is record
tcr_validate_o : std_logic;
tcr_disable_o : std_logic;
tcr_drop_ena_o : std_logic;
tsr0_qnt_o : std_logic_vector(15 downto 0);
tsr0_prio_o : std_logic_vector(7 downto 0);
tsr0_htai_o : std_logic_vector(7 downto 0);
tsr1_ltai_o : std_logic_vector(31 downto 0);
tsr2_cyc_o : std_logic_vector(27 downto 0);
tsr3_cyc_o : std_logic_vector(27 downto 0);
tsr4_ports_o : std_logic_vector(31 downto 0);
end record;
constant c_tatsu_out_registers_init_value: t_tatsu_out_registers := (
tcr_validate_o => '0',
tcr_disable_o => '0',
tcr_drop_ena_o => '0',
tsr0_qnt_o => (others => '0'),
tsr0_prio_o => (others => '0'),
tsr0_htai_o => (others => '0'),
tsr1_ltai_o => (others => '0'),
tsr2_cyc_o => (others => '0'),
tsr3_cyc_o => (others => '0'),
tsr4_ports_o => (others => '0')
);
function "or" (left, right: t_tatsu_in_registers) return t_tatsu_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body tatsu_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_tatsu_in_registers) return t_tatsu_in_registers is
variable tmp: t_tatsu_in_registers;
begin
tmp.tcr_min_rpt_i := f_x_to_zero(left.tcr_min_rpt_i) or f_x_to_zero(right.tcr_min_rpt_i);
tmp.tcr_started_i := f_x_to_zero(left.tcr_started_i) or f_x_to_zero(right.tcr_started_i);
tmp.tcr_delayed_i := f_x_to_zero(left.tcr_delayed_i) or f_x_to_zero(right.tcr_delayed_i);
tmp.tcr_stg_ok_i := f_x_to_zero(left.tcr_stg_ok_i) or f_x_to_zero(right.tcr_stg_ok_i);
tmp.tcr_stg_err_i := f_x_to_zero(left.tcr_stg_err_i) or f_x_to_zero(right.tcr_stg_err_i);
tmp.tcr_stg_err_tai_i := f_x_to_zero(left.tcr_stg_err_tai_i) or f_x_to_zero(right.tcr_stg_err_tai_i);
tmp.tcr_stg_err_cyc_i := f_x_to_zero(left.tcr_stg_err_cyc_i) or f_x_to_zero(right.tcr_stg_err_cyc_i);
tmp.tcr_stg_err_rpt_i := f_x_to_zero(left.tcr_stg_err_rpt_i) or f_x_to_zero(right.tcr_stg_err_rpt_i);
tmp.tcr_stg_err_snc_i := f_x_to_zero(left.tcr_stg_err_snc_i) or f_x_to_zero(right.tcr_stg_err_snc_i);
return tmp;
end function;
end package body;
modules/wrsw_tatsu/tatsu_wishbone_controller.vhd 0 → 100644
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modules/wrsw_tatsu/tatsu_wishbone_controller.wb 0 → 100644
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-- -*- Mode: LUA; tab-width: 2 -*-
-------------------------------------------------------------------------------
-- Title : Wishbone Register Block (slave)
-- Project : White Rabbit Time Aware Traffic Shaper
-------------------------------------------------------------------------------
-- File : tatsu_wishbone_controller.wb
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2013-03-01
-- Last update: 2013-03-01
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1l.html
--
-------------------------------------------------------------------------------
peripheral {
name = "WR switch Time Aware Traffic Shaper controller";
description = "TATSU controller";
hdl_entity = "tatsu_wishbone_controller";
prefix = "tatsu";
-- ECR
reg {
name = "TATSU Control Register/Status";
prefix = "TCR";
description = "General TATSU control and status register";
field {
name = "Validate new settings, enable TATSU (if disabled)";
description = "1: validates settings and enables TATSU\
0: does nothing";
prefix = "VALIDATE";
type = MONOSTABLE;
};
field {
name = "Stop TATSU";
description = "1: disables Time Aware Traffic Shapper\
0: does nothing ";
prefix = "DISABLE";
type = MONOSTABLE;
};
field {
name = "Drop no-HP at HP";
description = "Drop transmitted frame when frame with high priority awaits transmission\
1: Enable feature\
0: Disable feature";
prefix = "DROP_ENA";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Min repeat value";
description = "Repeats the minimum repeat value which can be set";
prefix = "MIN_RPT";
type = SLV;
size = 8;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TATSU started";
description = "1: TATSU is running with the validated settings (the set time has been already reached, now we repeat)\
0: TATSU is not running (probably waiting for the time";
prefix = "STARTED";
type = BIT;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Delayed start";
description = "1: The time indicated with the settings as a start has been missed (time adjustment at this particular time) so the start is attempted repeat_cycles later (if attemt successful, the STARTED bit is set)\
0: Normal start";
prefix = "DELAYED";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Settings OK";
description = "1: The settings has been validated succesfully\
0: If checked after asserting VALIDATE it indicates that settings where not accepted -- the error bit is probably set and indicaes what went wrokng)";
prefix = "STG_OK";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Settings Error";
description = "1: Indicates Shapers error - check other error bits for details\
0: Shaper seems to be working OK";
prefix = "STG_ERR";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Settings Error: TAI value";
description = "1: Error triggered by wrong TAI value (probably you tried to set time in the past)\
0: TAI value OK";
prefix = "STG_ERR_TAI";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Settings Error: cycle value";
description = "1: Error triggered by wrong cycle value\
0: Cycle value OK";
prefix = "STG_ERR_CYC";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Settings Error: repeat value";
description = "1: Error triggered by wrong repeat value (too small or too big)\
0: Repeat value OK";
prefix = "STG_ERR_RPT";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Internal Time Sync Error";
description = "1: Shaper stopped working due to the error with synchronizing internal counter with time soruce (tm_cycle_i), this is because the tm_time_valid_i was too long down)\
0: Time Sync OK";
prefix = "STG_ERR_SNC";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-- TSR
reg {
name = "TATSU Settings Register 0";
prefix = "TSR0";
description = "TATSU Settings register 0";
field {
name = "Quanta";
description = "Window length (time measured in quanta=512 bits time)";
prefix = "QNT";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Window Priorit Mask";
description = "Mask which indicates which priorities (Classe of Service) are allowed within the window\
1 at bit N - indicates that traffic on priority N is allowed during Window\
0 at bit N - indicates that traffic on priority N is blocked during Window";
prefix = "prio";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Start time (hi_TAI)";
description = "Start time: high bits of the TAI value [39:32]";
prefix = "hTAI";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TATSU Settings Register 1";
prefix = "TSR1";
description = "TATSU Settings register 1";
field {
name = "Start time (lo_TAI)";
description = "Start timeLow bits of the TAI value [31:0]";
prefix = "lTAI";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TATSU Settings Register 2";
prefix = "TSR2";
description = "TATSU Settings register 2";
field {
name = "Start time (cycles)";
description = "Start time: cycles part of time";
prefix = "cyc";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TATSU Settings Register 3";
prefix = "TSR3";
description = "TATSU Settings register 3";
field {
name = "Repeat time (cycle)";
description = "Repeat time: defines (in cycles units) how often the window shall be repeated";
prefix = "cyc";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TATSU Settings Register 4";
prefix = "TSR4";
description = "TATSU Settings register 4";
field {
name = "Ports mask";
description = "Mask which indicated which ports shall be affected by the shaper";
prefix = "ports";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
\ No newline at end of file
modules/wrsw_tatsu/wrsw_tatsu_pkg.vhd 0 → 100644
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-------------------------------------------------------------------------------
-- Title : Time-Aware Traffic Shaper Unit: package
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : wrsw_tatsu_pkg.vhd
-- Author : Maciej Lipinski
-- Company : CERN BE-CO-HT
-- Created : 2013-03-01
-- Last update: 2012-03-01
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Package with records, function, constants and components
-- declarations for TATSU module
--
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
--
--
--
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 Maciej Lipinski / CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-03-01 1.0 mlipinsk Created
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
library work;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.CEIL;
use ieee.math_real.log2;
use work.wrsw_shared_types_pkg.all;
use work.tatsu_wbgen2_pkg.all;
use work.wishbone_pkg.all; -- wishbone_{interface_mode,address_granularity}
package wrsw_tatsu_pkg is
type t_tatsu_config is record
start_tm_tai : std_logic_vector(39 downto 0);
start_tm_cycles : std_logic_vector(27 downto 0);
repeat_cycles : std_logic_vector(27 downto 0);
window_quanta : std_logic_vector(15 downto 0);
ports_mask : std_logic_vector(31 downto 0);
prio_mask : std_logic_vector(7 downto 0);
end record;
component tatsu_wishbone_controller is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_tatsu_in_registers;
regs_o : out t_tatsu_out_registers
);
end component;
component xwrsw_tatsu is
generic(
g_num_ports : integer := 6;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_simulation : boolean := false;
g_address_granularity: t_wishbone_address_granularity := BYTE
);
port (
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_i : in std_logic;
shaper_request_o : out t_pause_request ;
shaper_ports_o : out std_logic_vector(g_num_ports-1 downto 0);
shaper_drop_at_hp_ena_o : out std_logic;
tm_utc_i : in std_logic_vector(39 downto 0);
tm_cycles_i : in std_logic_vector(27 downto 0);
tm_time_valid_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out
);
end component;
function f_pick (
cond : boolean;
if_true : integer;
if_false : integer
) return integer;
end wrsw_tatsu_pkg;
package body wrsw_tatsu_pkg is
function f_pick (
cond : boolean;
if_true : integer;
if_false : integer
) return integer is
begin
if(cond) then
return if_true;
else
return if_false;
end if;
end f_pick;
end wrsw_tatsu_pkg;
modules/wrsw_tatsu/xwrsw_tatsu.vhd 0 → 100644
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sim/regs/tatsu_regs.v 0 → 100644
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`define ADDR_TATSU_TCR 5'h0
`define TATSU_TCR_VALIDATE_OFFSET 0
`define TATSU_TCR_VALIDATE 32'h00000001
`define TATSU_TCR_DISABLE_OFFSET 1
`define TATSU_TCR_DISABLE 32'h00000002
`define TATSU_TCR_DROP_ENA_OFFSET 8
`define TATSU_TCR_DROP_ENA 32'h00000100
`define TATSU_TCR_MIN_RPT_OFFSET 16
`define TATSU_TCR_MIN_RPT 32'h00ff0000
`define TATSU_TCR_STARTED_OFFSET 24
`define TATSU_TCR_STARTED 32'h01000000
`define TATSU_TCR_DELAYED_OFFSET 25
`define TATSU_TCR_DELAYED 32'h02000000
`define TATSU_TCR_STG_OK_OFFSET 26
`define TATSU_TCR_STG_OK 32'h04000000
`define TATSU_TCR_STG_ERR_OFFSET 27
`define TATSU_TCR_STG_ERR 32'h08000000
`define TATSU_TCR_STG_ERR_TAI_OFFSET 28
`define TATSU_TCR_STG_ERR_TAI 32'h10000000
`define TATSU_TCR_STG_ERR_CYC_OFFSET 29
`define TATSU_TCR_STG_ERR_CYC 32'h20000000
`define TATSU_TCR_STG_ERR_RPT_OFFSET 30
`define TATSU_TCR_STG_ERR_RPT 32'h40000000
`define TATSU_TCR_STG_ERR_SNC_OFFSET 31
`define TATSU_TCR_STG_ERR_SNC 32'h80000000
`define ADDR_TATSU_TSR0 5'h4
`define TATSU_TSR0_QNT_OFFSET 0
`define TATSU_TSR0_QNT 32'h0000ffff
`define TATSU_TSR0_PRIO_OFFSET 16
`define TATSU_TSR0_PRIO 32'h00ff0000
`define TATSU_TSR0_HTAI_OFFSET 24
`define TATSU_TSR0_HTAI 32'hff000000
`define ADDR_TATSU_TSR1 5'h8
`define TATSU_TSR1_LTAI_OFFSET 0
`define TATSU_TSR1_LTAI 32'hffffffff
`define ADDR_TATSU_TSR2 5'hc
`define TATSU_TSR2_CYC_OFFSET 0
`define TATSU_TSR2_CYC 32'h0fffffff
`define ADDR_TATSU_TSR3 5'h10
`define TATSU_TSR3_CYC_OFFSET 0
`define TATSU_TSR3_CYC 32'h0fffffff
`define ADDR_TATSU_TSR4 5'h14
`define TATSU_TSR4_PORTS_OFFSET 0
`define TATSU_TSR4_PORTS 32'hffffffff
sim/simdrv_tatsu.svh 0 → 100644
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`ifndef __SIMDRV_WR_TATSU
`define __SIMDRV_WR_TATSU 1
`timescale 1ns/1ps
`include "simdrv_defs.svh"
`include "regs/tatsu_regs.v"
class CSimDrv_TATSU;
protected CBusAccessor m_acc;
protected uint64_t m_base;
function new(CBusAccessor acc, uint64_t base, bit dbg=0);
m_acc = acc;
m_base = base;
endfunction // new
task set_tatsu(bit[15:0] quanta, bit[39:0] tm_tai, bit[27:0] tm_cycles,
bit[ 7:0] prio_mask, bit[31:0] port_mask, bit[27:0] repeat_cycles);
m_acc.write(m_base + `ADDR_TATSU_TSR0,
(tm_tai[39:32] << `TATSU_TSR0_HTAI_OFFSET) & `TATSU_TSR0_HTAI |
(prio_mask << `TATSU_TSR0_PRIO_OFFSET) & `TATSU_TSR0_PRIO |
(quanta << `TATSU_TSR0_QNT_OFFSET) & `TATSU_TSR0_QNT );
m_acc.write(m_base + `ADDR_TATSU_TSR1, tm_tai[31:0]);
m_acc.write(m_base + `ADDR_TATSU_TSR2, tm_cycles);
m_acc.write(m_base + `ADDR_TATSU_TSR3, repeat_cycles & `TATSU_TSR3_CYC );
m_acc.write(m_base + `ADDR_TATSU_TSR4, port_mask);
m_acc.write(m_base + `ADDR_TATSU_TCR, `TATSU_TCR_VALIDATE);
endtask;
task drop_at_HP_enable();
uint64_t tmp;
m_acc.read(m_base + `ADDR_TATSU_TCR, tmp, 4);
m_acc.write(m_base + `ADDR_TATSU_TSR0, tmp | `TATSU_TCR_DROP_ENA);
$display("TATSU: enable drop at HP");
endtask;
task drop_at_HP_disable();
uint64_t tmp;
m_acc.read(m_base + `ADDR_TATSU_TCR, tmp, 4);
m_acc.write(m_base + `ADDR_TATSU_TSR0, tmp & ~(`TATSU_TCR_DROP_ENA));
$display("TATSU: disable drop at HP");
endtask;
// task get_status(output int OK, output int error);
// uint64_t tmp;
//
// m_acc.read(m_base + `ADDR_TATSU_TCR, tmp, 4);
// OK = (tmp & `TATSU_TCR_OK) >> `TATSU_TCR_OK_OFFSET;
// error = (tmp & `TATSU_TCR_ERROR) >> `TATSU_TCR_ERROR_OFFSET;
// $display("TATSU status: OK=%1d Error=%1d", OK, error);
//
// endtask;
task print_status();
uint64_t tmp;
int OK, error;
m_acc.read(m_base + `ADDR_TATSU_TCR, tmp, 4);
$display("TATSU status: [raw=x%x]",tmp);
if(tmp & `TATSU_TCR_STARTED) $display("\t TATSU started");
if(tmp & `TATSU_TCR_DELAYED) $display("\t TATSU starte delayed");
if(tmp & `TATSU_TCR_STG_ERR) $display("\t ERROR");
if(tmp & `TATSU_TCR_STG_OK) $display("\t Settings OK");
if(tmp & `TATSU_TCR_STG_ERR_TAI) $display("\t Settings ERROR: TAI value");
if(tmp & `TATSU_TCR_STG_ERR_CYC) $display("\t Settings ERROR: cycle value");
if(tmp & `TATSU_TCR_STG_ERR_RPT) $display("\t Settings ERROR: repeat value");
if(tmp & `TATSU_TCR_STG_ERR_SNC) $display("\t Sync ERROR");
endtask;
endclass // CSimDrv_TATSU
`endif // `ifndef __SIMDRV_TATSU_SVH
testbench/scb_top/main.sv
View file @ 22382623
This diff is collapsed.
top/bare_top/scb_top_bare.vhd
View file @ 22382623
......@@ -13,6 +13,7 @@ use work.wrsw_txtsu_pkg.all;
use work.wrsw_top_pkg.all;
use work.wrsw_shared_types_pkg.all;
use work.wrsw_tru_pkg.all;
use work.wrsw_tatsu_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
......@@ -22,7 +23,8 @@ entity scb_top_bare is
g_num_ports : integer := 6;
g_simulation : boolean := false;
g_without_network : boolean := false;
g_with_TRU : boolean := false
g_with_TRU : boolean := false;
g_with_TATSU : boolean := false
);
port (
sys_rst_n_i : in std_logic; -- global reset
......@@ -128,7 +130,7 @@ end scb_top_bare;
architecture rtl of scb_top_bare is
constant c_NUM_WB_SLAVES : integer := 11;
constant c_NUM_WB_SLAVES : integer := 12;
constant c_NUM_PORTS : integer := g_num_ports;
constant c_MAX_PORTS : integer := 18;
......@@ -148,9 +150,11 @@ architecture rtl of scb_top_bare is
constant c_SLAVE_MBL_I2C1 : integer := 8;
constant c_SLAVE_SENSOR_I2C : integer := 9;
constant c_SLAVE_TRU : integer := 10;
constant c_SLAVE_TATSU : integer := 11;
constant c_cnx_base_addr : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0) :=
(
x"00058000", -- TATSU
x"00057000", -- TRU
x"00056000", -- Sensors-I2C
x"00055000", -- MBL-I2C1
......@@ -166,6 +170,7 @@ architecture rtl of scb_top_bare is
constant c_cnx_base_mask : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0) :=
(x"000ff000",
x"000ff000",
x"000ff000",
x"000ff000",
x"000ff000",
......@@ -320,6 +325,19 @@ architecture rtl of scb_top_bare is
signal tru2ep : t_tru2ep_array(g_num_ports-1 downto 0);
signal swc2tru : std_logic_vector(g_num_ports-1 downto 0); -- for pausing
-----------------------------------------------------------------------------
-- Time-Aware Traffic Shaper
-----------------------------------------------------------------------------
signal tm_utc : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_time_valid : std_logic;
signal shaper_ports_mask : std_logic_vector(g_num_ports+1-1 downto 0);
signal shaper_request : t_pause_request;
signal shaper_drop_at_hp_ena : std_logic;
signal fc_rx_pause : t_pause_request_array(g_num_ports+1-1 downto 0);
constant c_zero_pause : t_pause_request :=('0',x"0000", x"00");
begin
......@@ -427,6 +445,11 @@ begin
pps_ext_o => pps_o,
sel_clk_sys_o => sel_clk_sys,
tm_utc_o => tm_utc,
tm_cycles_o => tm_cycles,
tm_time_valid_o => tm_time_valid,
pll_status_i => '0',
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
......@@ -468,8 +491,10 @@ begin
rtu_rsp_ack_i => rtu_rsp_ack(c_NUM_PORTS),
wb_i => cnx_master_out(c_SLAVE_NIC),
wb_o => cnx_master_in(c_SLAVE_NIC));
fc_rx_pause(c_NUM_PORTS) <= c_zero_pause; -- no pause for NIC
shaper_ports_mask(c_NUM_PORTS) <= '0';
U_Endpoint_Fanout : xwb_crossbar
generic map (
g_num_masters => 1,
......@@ -554,15 +579,19 @@ begin
pfilter_pclass_o => ep2tru(i).pfilter_pclass,
pfilter_drop_o => ep2tru(i).pfilter_drop,
pfilter_done_o => ep2tru(i).pfilter_done,
fc_pause_req_i => tru2ep(i).fc_pause_req,
fc_pause_delay_i => tru2ep(i).fc_pause_delay,
fc_pause_ready_o => ep2tru(i).fc_pause_ready,
fc_tx_pause_req_i => tru2ep(i).fc_pause_req,
fc_tx_pause_delay_i => tru2ep(i).fc_pause_delay,
fc_tx_pause_ready_o => ep2tru(i).fc_pause_ready,
inject_req_i => tru2ep(i).inject_req,
inject_ready_o => ep2tru(i).inject_ready,
inject_packet_sel_i => tru2ep(i).inject_packet_sel,
inject_user_value_i => tru2ep(i).inject_user_value,
link_kill_i => tru2ep(i).link_kill, --'0' , --link_kill(i), -- to change
link_up_o => ep2tru(i).status,
------ PAUSE to SWcore ------------
fc_rx_pause_start_p_o => fc_rx_pause(i).req,
fc_rx_pause_quanta_o => fc_rx_pause(i).quanta,
fc_rx_pause_prio_mask_o => fc_rx_pause(i).classes,
----------------------------
led_link_o => led_link_o(i),
led_act_o => led_act_o(i));
......@@ -631,10 +660,16 @@ begin
snk_i => endpoint_src_out,
snk_o => endpoint_src_in,
shaper_request_i => shaper_request,
shaper_ports_i => shaper_ports_mask,
shaper_drop_at_hp_ena_i => shaper_drop_at_hp_ena,
pause_requests_i => fc_rx_pause,
rtu_rsp_i => rtu_rsp,
rtu_ack_o => rtu_rsp_ack
);
-- NIC sink
--TRIG0 <= f_fabric_2_slv(endpoint_snk_in(1), endpoint_snk_out(1));
---- NIC source
......@@ -710,6 +745,40 @@ begin
cnx_master_in(c_SLAVE_TRU).ack <= '1';
end generate gen_no_TRU;
gen_TATSU: if(g_with_TATSU = true) generate
U_TATSU: xwrsw_tatsu
generic map(
g_num_ports => g_num_ports,
g_simulation => g_simulation,
g_interface_mode => PIPELINED,
-- g_ref_clock_rate => f_pick(g_simulation, 10000, 62500000),
g_address_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
clk_ref_i => clk_ref_i,
rst_n_i => rst_n_sys,
shaper_request_o => shaper_request,
shaper_ports_o => shaper_ports_mask(g_num_ports-1 downto 0),
shaper_drop_at_hp_ena_o => shaper_drop_at_hp_ena,
tm_utc_i => tm_utc,
tm_cycles_i => tm_cycles,
tm_time_valid_i => tm_time_valid,
wb_i => cnx_master_out(c_SLAVE_TATSU),
wb_o => cnx_master_in(c_SLAVE_TATSU)
);
end generate gen_TATSU;
gen_no_TATSU: if(g_with_TATSU = false) generate
shaper_ports_mask(g_num_ports-1 downto 0) <= (others =>'0');
shaper_request <= c_zero_pause;
shaper_drop_at_hp_ena <= '0';
cnx_master_in(c_SLAVE_TATSU).ack <= '1';
end generate gen_no_TATSU;
end generate gen_network_stuff;
gen_no_network_stuff : if(g_without_network = true) generate
......
top/bare_top/scb_top_sim.vhd
View file @ 22382623
......@@ -138,7 +138,8 @@ begin -- rtl
g_num_ports => g_num_ports,
g_simulation => true,
g_without_network => false,
g_with_TRU => true)
g_with_TRU => true,
g_with_TATSU => true)
port map (
sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_startup_i,
......
top/bare_top/wrsw_components_pkg.vhd
View file @ 22382623
......@@ -180,6 +180,9 @@ package wrsw_components_pkg is
pps_p_o : out std_logic;
pps_raw_i : in std_logic;
sel_clk_sys_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
......@@ -239,7 +242,12 @@ package wrsw_components_pkg is
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0);
src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
shaper_request_i : in t_pause_request ;
shaper_ports_i : in std_logic_vector(g_num_ports-1 downto 0);
shaper_drop_at_hp_ena_i : in std_logic := '0';
pause_requests_i : in t_pause_request_array(g_num_ports-1 downto 0);
rtu_rsp_i : in t_rtu_response_array(g_num_ports - 1 downto 0);
rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0)
);
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 22382623
......@@ -185,6 +185,9 @@ package wrsw_top_pkg is
pps_ext_i : in std_logic;
pps_ext_o : out std_logic;
sel_clk_sys_o : out std_logic;
tm_utc_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_time_valid_o : out std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
......@@ -216,7 +219,8 @@ package wrsw_top_pkg is
g_num_ports : integer;
g_simulation : boolean;
g_without_network : boolean;
g_with_TRU : boolean := false);
g_with_TRU : boolean := false;
g_with_TATSU : boolean := false);
port (
sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic;
......@@ -291,6 +295,11 @@ package wrsw_top_pkg is
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0);
src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
shaper_request_i : in t_pause_request ;
shaper_ports_i : in std_logic_vector(g_num_ports-1 downto 0);
shaper_drop_at_hp_ena_i : in std_logic := '0';
pause_requests_i : in t_pause_request_array(g_num_ports-1 downto 0);
rtu_rsp_i : in t_rtu_response_array(g_num_ports - 1 downto 0);
rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0)
);
......
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