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White Rabbit Switch - Gateware
Commit 233c4b19 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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v4-dev: wrsw_nic: sw reset can be a single monostable bit instead of using *_wr… 

v4-dev: wrsw_nic: sw reset can be a single monostable bit instead of using *_wr signal from the whole register
parent 1455df43
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modules/wrsw_nic/nic_wbgen2_pkg.vhd
View file @ 233c4b19
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : nic_wbgen2_pkg.vhd -- File : nic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb -- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created : Thu Mar 28 08:35:23 2013 -- Created : Thu Mar 28 09:24:42 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
...@@ -43,27 +43,25 @@ package nic_wbgen2_pkg is ...@@ -43,27 +43,25 @@ package nic_wbgen2_pkg is
type t_nic_out_registers is record type t_nic_out_registers is record
cr_rx_en_o : std_logic; cr_rx_en_o : std_logic;
cr_tx_en_o : std_logic; cr_tx_en_o : std_logic;
cr_sw_rst_o : std_logic;
sr_rec_o : std_logic; sr_rec_o : std_logic;
sr_rec_load_o : std_logic; sr_rec_load_o : std_logic;
sr_tx_done_o : std_logic; sr_tx_done_o : std_logic;
sr_tx_done_load_o : std_logic; sr_tx_done_load_o : std_logic;
sr_tx_error_o : std_logic; sr_tx_error_o : std_logic;
sr_tx_error_load_o : std_logic; sr_tx_error_load_o : std_logic;
reset_o : std_logic_vector(31 downto 0);
reset_wr_o : std_logic;
end record; end record;
constant c_nic_out_registers_init_value: t_nic_out_registers := ( constant c_nic_out_registers_init_value: t_nic_out_registers := (
cr_rx_en_o => '0', cr_rx_en_o => '0',
cr_tx_en_o => '0', cr_tx_en_o => '0',
cr_sw_rst_o => '0',
sr_rec_o => '0', sr_rec_o => '0',
sr_rec_load_o => '0', sr_rec_load_o => '0',
sr_tx_done_o => '0', sr_tx_done_o => '0',
sr_tx_done_load_o => '0', sr_tx_done_load_o => '0',
sr_tx_error_o => '0', sr_tx_error_o => '0',
sr_tx_error_load_o => '0', sr_tx_error_load_o => '0'
reset_o => (others => '0'),
reset_wr_o => '0'
); );
function "or" (left, right: t_nic_in_registers) return t_nic_in_registers; function "or" (left, right: t_nic_in_registers) return t_nic_in_registers;
function f_x_to_zero (x:std_logic) return std_logic; function f_x_to_zero (x:std_logic) return std_logic;
......
modules/wrsw_nic/nic_wishbone_slave.vhd
View file @ 233c4b19
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : nic_wishbone_slave.vhd -- File : nic_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb -- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created : Thu Mar 28 08:35:23 2013 -- Created : Thu Mar 28 09:24:42 2013
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
...@@ -69,6 +69,8 @@ architecture syn of nic_wishbone_slave is ...@@ -69,6 +69,8 @@ architecture syn of nic_wishbone_slave is
signal nic_cr_rx_en_int : std_logic ; signal nic_cr_rx_en_int : std_logic ;
signal nic_cr_tx_en_int : std_logic ; signal nic_cr_tx_en_int : std_logic ;
signal nic_cr_sw_rst_dly0 : std_logic ;
signal nic_cr_sw_rst_int : std_logic ;
signal nic_dtx_rddata_int : std_logic_vector(31 downto 0); signal nic_dtx_rddata_int : std_logic_vector(31 downto 0);
signal nic_dtx_rd_int : std_logic ; signal nic_dtx_rd_int : std_logic ;
signal nic_dtx_wr_int : std_logic ; signal nic_dtx_wr_int : std_logic ;
...@@ -114,10 +116,10 @@ begin ...@@ -114,10 +116,10 @@ begin
rddata_reg <= "00000000000000000000000000000000"; rddata_reg <= "00000000000000000000000000000000";
nic_cr_rx_en_int <= '0'; nic_cr_rx_en_int <= '0';
nic_cr_tx_en_int <= '0'; nic_cr_tx_en_int <= '0';
nic_cr_sw_rst_int <= '0';
regs_o.sr_rec_load_o <= '0'; regs_o.sr_rec_load_o <= '0';
regs_o.sr_tx_done_load_o <= '0'; regs_o.sr_tx_done_load_o <= '0';
regs_o.sr_tx_error_load_o <= '0'; regs_o.sr_tx_error_load_o <= '0';
regs_o.reset_wr_o <= '0';
eic_idr_write_int <= '0'; eic_idr_write_int <= '0';
eic_ier_write_int <= '0'; eic_ier_write_int <= '0';
eic_isr_write_int <= '0'; eic_isr_write_int <= '0';
...@@ -127,10 +129,10 @@ begin ...@@ -127,10 +129,10 @@ begin
ack_sreg(9) <= '0'; ack_sreg(9) <= '0';
if (ack_in_progress = '1') then if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then if (ack_sreg(0) = '1') then
nic_cr_sw_rst_int <= '0';
regs_o.sr_rec_load_o <= '0'; regs_o.sr_rec_load_o <= '0';
regs_o.sr_tx_done_load_o <= '0'; regs_o.sr_tx_done_load_o <= '0';
regs_o.sr_tx_error_load_o <= '0'; regs_o.sr_tx_error_load_o <= '0';
regs_o.reset_wr_o <= '0';
eic_idr_write_int <= '0'; eic_idr_write_int <= '0';
eic_ier_write_int <= '0'; eic_ier_write_int <= '0';
eic_isr_write_int <= '0'; eic_isr_write_int <= '0';
...@@ -139,7 +141,6 @@ begin ...@@ -139,7 +141,6 @@ begin
regs_o.sr_rec_load_o <= '0'; regs_o.sr_rec_load_o <= '0';
regs_o.sr_tx_done_load_o <= '0'; regs_o.sr_tx_done_load_o <= '0';
regs_o.sr_tx_error_load_o <= '0'; regs_o.sr_tx_error_load_o <= '0';
regs_o.reset_wr_o <= '0';
end if; end if;
else else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
...@@ -150,9 +151,11 @@ begin ...@@ -150,9 +151,11 @@ begin
if (wb_we_i = '1') then if (wb_we_i = '1') then
nic_cr_rx_en_int <= wrdata_reg(0); nic_cr_rx_en_int <= wrdata_reg(0);
nic_cr_tx_en_int <= wrdata_reg(1); nic_cr_tx_en_int <= wrdata_reg(1);
nic_cr_sw_rst_int <= wrdata_reg(31);
end if; end if;
rddata_reg(0) <= nic_cr_rx_en_int; rddata_reg(0) <= nic_cr_rx_en_int;
rddata_reg(1) <= nic_cr_tx_en_int; rddata_reg(1) <= nic_cr_tx_en_int;
rddata_reg(31) <= 'X';
rddata_reg(2) <= 'X'; rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X'; rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X'; rddata_reg(4) <= 'X';
...@@ -182,8 +185,7 @@ begin ...@@ -182,8 +185,7 @@ begin
rddata_reg(28) <= 'X'; rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X'; ack_sreg(2) <= '1';
ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "0001" => when "0001" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
...@@ -221,44 +223,6 @@ begin ...@@ -221,44 +223,6 @@ begin
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
regs_o.reset_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" => when "1000" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
eic_idr_write_int <= '1'; eic_idr_write_int <= '1';
...@@ -474,6 +438,19 @@ begin ...@@ -474,6 +438,19 @@ begin
regs_o.cr_rx_en_o <= nic_cr_rx_en_int; regs_o.cr_rx_en_o <= nic_cr_rx_en_int;
-- Transmit enable -- Transmit enable
regs_o.cr_tx_en_o <= nic_cr_tx_en_int; regs_o.cr_tx_en_o <= nic_cr_tx_en_int;
-- Software Reset
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
nic_cr_sw_rst_dly0 <= '0';
regs_o.cr_sw_rst_o <= '0';
elsif rising_edge(clk_sys_i) then
nic_cr_sw_rst_dly0 <= nic_cr_sw_rst_int;
regs_o.cr_sw_rst_o <= nic_cr_sw_rst_int and (not nic_cr_sw_rst_dly0);
end if;
end process;
-- Buffer Not Available -- Buffer Not Available
-- Frame Received -- Frame Received
regs_o.sr_rec_o <= wrdata_reg(1); regs_o.sr_rec_o <= wrdata_reg(1);
...@@ -483,9 +460,6 @@ begin ...@@ -483,9 +460,6 @@ begin
regs_o.sr_tx_error_o <= wrdata_reg(3); regs_o.sr_tx_error_o <= wrdata_reg(3);
-- Current TX descriptor -- Current TX descriptor
-- Current RX descriptor -- Current RX descriptor
-- Software reset
-- pass-through field: Software reset in register: SW_Reset
regs_o.reset_o <= wrdata_reg(31 downto 0);
-- extra code for reg/fifo/mem: TX descriptors mem -- extra code for reg/fifo/mem: TX descriptors mem
-- RAM block instantiation for memory: TX descriptors mem -- RAM block instantiation for memory: TX descriptors mem
nic_dtx_raminst : wbgen2_dpssram nic_dtx_raminst : wbgen2_dpssram
......
modules/wrsw_nic/wr_nic.wb
View file @ 233c4b19
...@@ -36,9 +36,6 @@ top = peripheral { ...@@ -36,9 +36,6 @@ top = peripheral {
* With EMPTY set to 0, the frame can now be copied from the NIC's memory and stats can be updated \ * With EMPTY set to 0, the frame can now be copied from the NIC's memory and stats can be updated \
* Set READY bit to 1 \ * Set READY bit to 1 \
\ \
Todo \
~~~~ \
* Descriptors in RAM, not as registers. wbgen2 doesn't support this yet. Working on it. \
Known issues \ Known issues \
~~~~~~~~~~~ \ ~~~~~~~~~~~ \
* Only 32-bit aligned addresses are supported"; * Only 32-bit aligned addresses are supported";
...@@ -66,6 +63,16 @@ top = peripheral { ...@@ -66,6 +63,16 @@ top = peripheral {
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field {
name = "Software Reset";
description = "write 1: reset the NIC, zero all registers and reset the state of the module \
write 0: no effect";
prefix = "sw_rst";
size = 1;
align = 31;
type = MONOSTABLE;
};
}; };
reg { reg {
...@@ -145,18 +152,6 @@ top = peripheral { ...@@ -145,18 +152,6 @@ top = peripheral {
}; };
}; };
reg {
name = "SW_Reset";
description = "Writing to this register resets the NIC, zeroing all registers and resetting the state of the module";
prefix = "reset";
field {
name = "Software reset";
type = PASS_THROUGH;
size = 32;
};
};
irq { irq {
name = "Receive Complete"; name = "Receive Complete";
prefix = "rcomp"; prefix = "rcomp";
......
modules/wrsw_nic/xwrsw_nic.vhd
View file @ 233c4b19
...@@ -284,7 +284,7 @@ begin -- rtl ...@@ -284,7 +284,7 @@ begin -- rtl
wb_out.err <= '0'; wb_out.err <= '0';
wb_out.rty <= '0'; wb_out.rty <= '0';
nic_reset_n <= rst_n_i and (not regs_fromwb.reset_wr_o); nic_reset_n <= rst_n_i and (not regs_fromwb.cr_sw_rst_o);
regs_towb <= regs_towb_tx or regs_towb_rx or regs_towb_main; regs_towb <= regs_towb_tx or regs_towb_rx or regs_towb_main;
......
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