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White Rabbit Switch - Gateware
Commit 281d3676 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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chipscope for port 0 to debug link down lpdc issue

parent 149742fa
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top/bare_top/scb_top_bare.vhd
View file @ 281d3676
...@@ -355,7 +355,7 @@ architecture rtl of scb_top_bare is ...@@ -355,7 +355,7 @@ architecture rtl of scb_top_bare is
type t_trig is array(integer range <>) of std_logic_vector(31 downto 0); type t_trig is array(integer range <>) of std_logic_vector(31 downto 0);
signal control0 : std_logic_vector(35 downto 0); signal control0 : std_logic_vector(35 downto 0);
signal trig0, trig1, trig2, trig3 : t_trig(7 downto 0);--std_logic_vector(31 downto 0); --signal trig0, trig1, trig2, trig3 : t_trig(7 downto 0);--std_logic_vector(31 downto 0);
signal t0, t1, t2, t3 : std_logic_vector(31 downto 0); signal t0, t1, t2, t3 : std_logic_vector(31 downto 0);
signal rst_n_periph : std_logic; signal rst_n_periph : std_logic;
signal link_kill : std_logic_vector(c_NUM_PORTS-1 downto 0); signal link_kill : std_logic_vector(c_NUM_PORTS-1 downto 0);
...@@ -364,6 +364,8 @@ architecture rtl of scb_top_bare is ...@@ -364,6 +364,8 @@ architecture rtl of scb_top_bare is
signal swc_wdog_out : t_swc_fsms_array(c_NUM_PORTS downto 0); signal swc_wdog_out : t_swc_fsms_array(c_NUM_PORTS downto 0);
signal ep_stop_traffic : std_logic; signal ep_stop_traffic : std_logic;
signal ep_links_up : std_logic_vector(c_NUM_PORTS downto 0); signal ep_links_up : std_logic_vector(c_NUM_PORTS downto 0);
signal ep0_lup_synced : std_logic;
signal pps_in_synced : std_logic;
...@@ -415,6 +417,10 @@ architecture rtl of scb_top_bare is ...@@ -415,6 +417,10 @@ architecture rtl of scb_top_bare is
TRIG2 : in std_logic_vector(31 downto 0); TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)); TRIG3 : in std_logic_vector(31 downto 0));
end component; end component;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
signal gpio_out : std_logic_vector(c_NUM_GPIO_PINS-1 downto 0); signal gpio_out : std_logic_vector(c_NUM_GPIO_PINS-1 downto 0);
signal gpio_in : std_logic_vector(c_NUM_GPIO_PINS-1 downto 0); signal gpio_in : std_logic_vector(c_NUM_GPIO_PINS-1 downto 0);
...@@ -475,19 +481,61 @@ begin ...@@ -475,19 +481,61 @@ begin
--CS_ICON : chipscope_icon CS_ICON : chipscope_icon
-- port map ( port map (
-- CONTROL0 => CONTROL0); CONTROL0 => CONTROL0);
--CS_ILA : chipscope_ila CS_ILA : chipscope_ila
-- port map ( port map (
-- CONTROL => CONTROL0, CONTROL => CONTROL0,
-- CLK => clk_sys, CLK => phys_i(0).ref_clk,
-- TRIG0 => TRIG0, TRIG0 => TRIG0,
-- TRIG1 => TRIG1, TRIG1 => TRIG1,
-- TRIG2 => TRIG2, TRIG2 => TRIG2,
-- TRIG3 => TRIG3); TRIG3 => TRIG3);
TRIG0(15 downto 0) <= phys_i(0).rx_data;
TRIG0(17 downto 16) <= phys_i(0).rx_k;
TRIG0(18) <= phys_i(0).rx_enc_err;
TRIG0(19) <= ep0_lup_synced;
TRIG0(20) <= ep_links_up(0);
TRIG0(21) <= phys_i(0).lpc_stat(1);
TRIG0(31 downto 22) <= (others=>'0');
TRIG1(15 downto 0) <= phys_i(0).rx_data;
TRIG1(17 downto 16) <= phys_i(0).rx_k;
TRIG1(18) <= phys_i(0).rx_enc_err;
TRIG1(19) <= ep0_lup_synced;
TRIG1(20) <= ep_links_up(0);
TRIG1(21) <= phys_i(0).lpc_stat(1);
TRIG1(31 downto 22) <= (others=>'0');
TRIG2(15 downto 0) <= ep_dbg_data_array(0);
TRIG2(17 downto 16)<= ep_dbg_k_array(0);
TRIG2(18) <= pps_i;
TRIG2(19) <= pps_in_synced;
TRIG2(20) <= ep_links_up(0);
TRIG2(21) <= ep0_lup_synced;
TRIG2(31 downto 22) <= (others=>'0');
TRIG3(31 downto 0) <= (others=>'0');
pps_o <= phys_i(0).lpc_stat(1);
EX_TRIG_SYNC: gc_sync_ffs
port map(
clk_i => phys_i(0).ref_clk,
rst_n_i => '1',
data_i => pps_i,
synced_o => pps_in_synced);
LUP_SYNC: gc_sync_ffs
port map (
clk_i => phys_i(0).rx_clk,
rst_n_i => '1',
data_i => ep_links_up(0),
synced_o => ep0_lup_synced);
cnx_slave_in(0) <= cpu_wb_i; cnx_slave_in(0) <= cpu_wb_i;
cpu_wb_o <= cnx_slave_out(0); cpu_wb_o <= cnx_slave_out(0);
...@@ -647,7 +695,7 @@ begin ...@@ -647,7 +695,7 @@ begin
pps_csync_o => pps_csync, pps_csync_o => pps_csync,
pps_valid_o => pps_valid, pps_valid_o => pps_valid,
pps_ext_i => pps_i, pps_ext_i => '0', --pps_i,
ppsin_term_o=> ppsin_term_o, ppsin_term_o=> ppsin_term_o,
pps_ext_o => pps_o_predelay, pps_ext_o => pps_o_predelay,
...@@ -697,7 +745,7 @@ begin ...@@ -697,7 +745,7 @@ begin
REFCLK_FREQUENCY => 200.0, REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "DATA") SIGNAL_PATTERN => "DATA")
port map ( port map (
DATAOUT => pps_o, DATAOUT => open, --pps_o,
DATAIN => '0', DATAIN => '0',
C => clk_sys, C => clk_sys,
CE => '0', CE => '0',
...@@ -1310,24 +1358,24 @@ begin ...@@ -1310,24 +1358,24 @@ begin
swc_snk_in <= wrfreg_src_out; swc_snk_in <= wrfreg_src_out;
end generate; end generate;
gen_muxed_CS: if g_with_muxed_CS = true generate --gen_muxed_CS: if g_with_muxed_CS = true generate
CS_ICON : chipscope_icon -- CS_ICON : chipscope_icon
port map ( -- port map (
CONTROL0 => CONTROL0); -- CONTROL0 => CONTROL0);
CS_ILA : chipscope_ila -- CS_ILA : chipscope_ila
port map ( -- port map (
CONTROL => CONTROL0, -- CONTROL => CONTROL0,
CLK => clk_sys, --phys_i(0).rx_clk, -- CLK => clk_sys, --phys_i(0).rx_clk,
TRIG0 => T0, -- TRIG0 => T0,
TRIG1 => T1, -- TRIG1 => T1,
TRIG2 => T2, -- TRIG2 => T2,
TRIG3 => T3); -- TRIG3 => T3);
--
T0 <= TRIG0(to_integer(unsigned(dbg_chps_id))); -- T0 <= TRIG0(to_integer(unsigned(dbg_chps_id)));
T1 <= TRIG1(to_integer(unsigned(dbg_chps_id))); -- T1 <= TRIG1(to_integer(unsigned(dbg_chps_id)));
T2 <= TRIG2(to_integer(unsigned(dbg_chps_id))); -- T2 <= TRIG2(to_integer(unsigned(dbg_chps_id)));
T3 <= TRIG3(to_integer(unsigned(dbg_chps_id))); -- T3 <= TRIG3(to_integer(unsigned(dbg_chps_id)));
end generate; --end generate;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- WRS Low jitter daughterboard -- WRS Low jitter daughterboard
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ 281d3676
...@@ -352,8 +352,8 @@ NET "gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks"; ...@@ -352,8 +352,8 @@ NET "gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "gen_phys[3].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks"; NET "gen_phys[3].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "gen_phys[4].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks"; NET "gen_phys[4].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "gen_phys[5].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks"; NET "gen_phys[5].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "gen_phys[6].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks"; NET "gen_phys[6].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "gen_phys[7].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks"; NET "gen_phys[7].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "gen_phys[8].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks"; NET "gen_phys[8].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "gen_phys[9].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks"; NET "gen_phys[9].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "gen_phys[10].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks"; NET "gen_phys[10].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
...@@ -704,10 +704,10 @@ INST "gen_phys[4].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD; ...@@ -704,10 +704,10 @@ INST "gen_phys[4].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[4].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD; INST "gen_phys[4].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[5].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD; INST "gen_phys[5].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[5].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD; INST "gen_phys[5].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[6].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD; #INST "gen_phys[6].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[6].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD; #INST "gen_phys[6].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[7].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD; #INST "gen_phys[7].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[7].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD; #INST "gen_phys[7].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[8].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD; INST "gen_phys[8].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[8].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD; INST "gen_phys[8].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[9].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD; INST "gen_phys[9].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
...@@ -1475,8 +1475,8 @@ NET "gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[2].U_PHY/rx_r ...@@ -1475,8 +1475,8 @@ NET "gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[2].U_PHY/rx_r
NET "gen_phys[3].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[3].U_PHY/rx_rec_clk_bufin; NET "gen_phys[3].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[3].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[4].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].U_PHY/rx_rec_clk_bufin; NET "gen_phys[4].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[5].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[5].U_PHY/rx_rec_clk_bufin; NET "gen_phys[5].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[5].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[6].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[6].U_PHY/rx_rec_clk_bufin; NET "gen_phys[6].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[6].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[7].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[7].U_PHY/rx_rec_clk_bufin; NET "gen_phys[7].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[7].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[8].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[8].U_PHY/rx_rec_clk_bufin; NET "gen_phys[8].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[8].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[9].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[9].U_PHY/rx_rec_clk_bufin; NET "gen_phys[9].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[9].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[10].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[10].U_PHY/rx_rec_clk_bufin; NET "gen_phys[10].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[10].U_PHY/rx_rec_clk_bufin;
...@@ -1494,8 +1494,8 @@ TIMESPEC TS_gen_phys_2__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[2].gen_lp.U_PH ...@@ -1494,8 +1494,8 @@ TIMESPEC TS_gen_phys_2__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[2].gen_lp.U_PH
TIMESPEC TS_gen_phys_3__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[3].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_3__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[3].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_4__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_4__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_5__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[5].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_5__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[5].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_6__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[6].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_6__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[6].gen_no_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_7__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[7].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_7__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[7].gen_no_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_8__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[8].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_8__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[8].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_9__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[9].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_9__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[9].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_10__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[10].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_10__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[10].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
...@@ -1523,10 +1523,10 @@ NET "gen_phys[4].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[4].gen_lp.U_PHY ...@@ -1523,10 +1523,10 @@ NET "gen_phys[4].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[4].gen_lp.U_PHY
TIMESPEC TS_gen_phys_4__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[4].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_4__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[4].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[5].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[5].gen_lp.U_PHY/tx_out_clk_buf; NET "gen_phys[5].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[5].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_5__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[5].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_5__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[5].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[6].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[6].gen_lp.U_PHY/tx_out_clk_buf; #NET "gen_phys[6].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[6].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_6__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[6].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%; #TIMESPEC TS_gen_phys_6__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[6].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[7].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[7].gen_lp.U_PHY/tx_out_clk_buf; #NET "gen_phys[7].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[7].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_7__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[7].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%; #TIMESPEC TS_gen_phys_7__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[7].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[8].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[8].gen_lp.U_PHY/tx_out_clk_buf; NET "gen_phys[8].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[8].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_8__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[8].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_8__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[8].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[9].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[9].gen_lp.U_PHY/tx_out_clk_buf; NET "gen_phys[9].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[9].gen_lp.U_PHY/tx_out_clk_buf;
......
top/scb_18ports/scb_top_synthesis.vhd
View file @ 281d3676
...@@ -476,8 +476,8 @@ architecture Behavioral of scb_top_synthesis is ...@@ -476,8 +476,8 @@ architecture Behavioral of scb_top_synthesis is
3 => true, 3 => true,
4 => true, 4 => true,
5 => true, 5 => true,
6 => true, 6 => false,
7 => true, 7 => false,
8 => true, 8 => true,
9 => true, 9 => true,
10 => true, 10 => true,
......
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