10mhz_gen: fix output level of the generated signal

LVDS was too low for the discrete flip-flop. This was creating spikes on low half of the signal on some switches.

10mhz_gen: fix output level of the generated signal
LVDS was too low for the discrete flip-flop. This was creating spikes on low half of the signal on some switches.
2d963063 · Grzegorz Daniluk · d58d268f · 2d963063
Commit 2d963063 authored Jul 07, 2015 by Grzegorz Daniluk
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oserdes_8_to_1.vhd platform/xilinx/oserdes_8_to_1.vhd +1 -1

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--- a/platform/xilinx/oserdes_8_to_1.vhd
+++ b/platform/xilinx/oserdes_8_to_1.vhd
@@ -144,7 +144,7 @@ begin
    -- Instantiate a buffer for every bit of the data bus
     obufds_inst : OBUFDS
       generic map (
-         IOSTANDARD => "LVDS_25")
+         IOSTANDARD => "LVPECL_25")
       port map (
         O          => DATA_OUT_TO_PINS_P  (pin_count),
         OB         => DATA_OUT_TO_PINS_N  (pin_count),