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Commit 31be1f04 authored by Maciej Lipinski's avatar Maciej Lipinski
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swcore[generic-azing]: generic simulation (for any number of ports) works,… 

swcore[generic-azing]: generic simulation (for any number of ports) works, cleaned up, added README to testbenches, changed names to add clarity to the naming
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modules/wrsw_swcore/swc_input_block.vhd deleted 100644 → 0
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modules/wrsw_swcore/swc_lost_pck_dealloc.vhd deleted 100644 → 0
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-------------------------------------------------------------------------------
-- Title : Lost Pck Deallocator
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : swc_lost_pck_dealloc.vhd
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-15
-- Last update: 2012-02-02
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
--
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2010 Maciej Lipinski / CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-15 1.0 mlipinsk Created
-- 2012-02-02 2.0 mlipinsk generic-azed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--use work.swc_swcore_pkg.all;
use work.genram_pkg.all;
entity swc_lost_pck_dealloc is
generic (
g_page_addr_width : integer --:= c_swc_page_addr_width;
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ib_force_free_i : in std_logic;
ib_force_free_done_o : out std_logic;
ib_force_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ob_force_free_i : in std_logic;
ob_force_free_done_o : out std_logic;
ob_force_free_pgaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_addr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
ll_read_data_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
ll_read_req_o : out std_logic;
ll_read_valid_data_i : in std_logic;
mmu_force_free_o : out std_logic;
mmu_force_free_done_i : in std_logic;
mmu_force_free_pgaddr_o : out std_logic_vector(g_page_addr_width -1 downto 0)
);
end swc_lost_pck_dealloc;
architecture syn of swc_lost_pck_dealloc is
type t_state is (S_IDLE,
S_REQ_READ_FIFO,
S_READ_FIFO,
S_READ_NEXT_PAGE_ADDR,
S_FREE_CURRENT_PAGE_ADDR
);
signal state : t_state;
signal ib_force_free_done : std_logic;
signal ob_force_free_done : std_logic;
signal fifo_wr : std_logic;
signal fifo_data_in : std_logic_vector(g_page_addr_width - 1 downto 0);
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_data_out : std_logic_vector(g_page_addr_width - 1 downto 0);
signal fifo_rd : std_logic;
signal fifo_clean : std_logic;
signal current_page : std_logic_vector(g_page_addr_width - 1 downto 0);
signal next_page : std_logic_vector(g_page_addr_width - 1 downto 0);
signal ll_read_req : std_logic;
signal mmu_force_free : std_logic;
signal ones : std_logic_vector(g_page_addr_width - 1 downto 0);
begin -- syn
ones <= (others => '1');
INPUT: process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
ib_force_free_done <= '0';
ob_force_free_done <= '0';
fifo_wr <= '0';
fifo_data_in <= (others => '0');
else
-- serve Input request, unless it's already served ( ib_force_free_done = '1')
if(ib_force_free_i = '1' and fifo_full = '0' and ib_force_free_done = '0') then
fifo_wr <= '1';
fifo_data_in <= ib_force_free_pgaddr_i;
ib_force_free_done <= '1';
ob_force_free_done <= '0';
elsif(ob_force_free_done = '1' and fifo_full = '0') then
fifo_wr <= '1';
fifo_data_in <= ob_force_free_pgaddr_i;
ob_force_free_done <= '1';
ib_force_free_done <= '0';
else
fifo_wr <= '0';
fifo_data_in <= (others => '0');
ib_force_free_done <= '0';
ob_force_free_done <= '0';
end if;
end if;
end if;
end process;
U_FIFO: generic_sync_fifo
generic map(
g_data_width => g_page_addr_width,
g_size => 16
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
we_i => fifo_wr,
d_i => fifo_data_in,
rd_i => fifo_rd,
q_o => fifo_data_out,
empty_o => fifo_empty,
full_o => fifo_full,
count_o => open
);
fsm_force_free : process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
--================================================
state <= S_IDLE;
fifo_rd <= '0';
current_page <= (others => '0');
next_page <= (others => '0');
ll_read_req <= '0';
mmu_force_free <= '0';
--================================================
else
-- main finite state machine
case state is
when S_IDLE =>
fifo_rd <= '0';
mmu_force_free <= '0';
if(fifo_empty = '0') then
fifo_rd <= '1';
state <= S_REQ_READ_FIFO;
end if;
when S_REQ_READ_FIFO =>
fifo_rd <= '0';
state <= S_READ_FIFO;
when S_READ_FIFO =>
current_page <= fifo_data_out;
ll_read_req <= '1';
state <= S_READ_NEXT_PAGE_ADDR;
when S_READ_NEXT_PAGE_ADDR =>
if(ll_read_valid_data_i = '1') then
ll_read_req <= '0';
state <= S_FREE_CURRENT_PAGE_ADDR;
next_page <= ll_read_data_i;
mmu_force_free <= '1';
end if;
when S_FREE_CURRENT_PAGE_ADDR =>
if(mmu_force_free_done_i = '1') then
mmu_force_free <= '0';
if(next_page = ones ) then
state <= S_IDLE;
else
current_page <= next_page;
ll_read_req <= '1';
state <= S_READ_NEXT_PAGE_ADDR;
end if;
end if;
when others =>
state <= S_IDLE;
fifo_rd <= '0';
current_page <= (others => '0');
next_page <= (others => '0');
ll_read_req <= '0';
mmu_force_free <= '0';
end case;
end if;
end if;
end process;
ll_read_addr_o <= current_page;
ll_read_req_o <= ll_read_req;
mmu_force_free_pgaddr_o <= current_page;
mmu_force_free_o <= mmu_force_free;
ib_force_free_done_o <= ib_force_free_done;
ob_force_free_done_o <= ob_force_free_done;
end syn;
modules/wrsw_swcore/swc_output_block.vhd deleted 100644 → 0
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testbench/swcore/Manifest.py
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......@@ -6,11 +6,11 @@ action = "simulation"
#files = "swc_core.v4.sv"
files = [
"xswc_core_7_ports_wrapper.vhd",
"xswcore_wrapper.svh",
"xswc_core.sv",
"xswcore_wrapper.v2.svh",
"xswc_core.v2.sv"
"swc_core_wrapper_7ports.vhd",
"xswc_core_wrapper_7ports.svh",
"swc_core_7ports.sv",
"swc_core_wrapper_generic.svh",
"swc_core_generic.sv"
]
#vlog_opt="+incdir+../../../sim "
......
testbench/swcore/README 0 → 100644
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-------------------------------------------------------------------------------
-- Title : README on testbenches
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : README
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2012-02-07
-- Last update: 2012-02-07
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-01-15 1.0 mlipinsk Created
-------------------------------------------------------------------------------
Currently used testbenches:
1. Generic
- it can be used for any number of ports, the number of ports is defined in swc_param_defs.svh
- it uses the parameters (i.e. number of ports) defined in swc_param_defs.svh
- simulate with: vsim main_generic
swc_core_generic.sv
|-> swc_core_wrapper_generic.svh
|-> swc_core.vhd
2. 7 ports
- it simulates swcore configured for 7 ports
- it uses hand made wrapper
- simulat with: vsim main_7ports
swc_core_7ports.sv
|->xswc_core_wrapper_7ports.svh
|->swc_core_wrapper_7ports.vhd
|->xswc_core.vhd
Currently unused testbenches [not tested if work]: all the rest (they might be useful for further
single components verification and tests later)
\ No newline at end of file
testbench/swcore/swc_core.sv deleted 100644 → 0
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testbench/swcore/swc_core.v2.sv deleted 100644 → 0
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testbench/swcore/swc_core.v3.sv deleted 100644 → 0
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testbench/swcore/swc_core.v4.sv deleted 100644 → 0
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testbench/swcore/xswc_core.sv → testbench/swcore/swc_core_7ports.sv
View file @ 31be1f04
......@@ -16,7 +16,7 @@
`include "wb_packet_source.svh"
`include "wb_packet_sink.svh"
`include "xswcore_wrapper.svh"
`include "xswc_core_wrapper_7ports.svh"
typedef struct {
......@@ -39,7 +39,7 @@ int pg_dealloc_cnt[1024][20];
EthPacket swc_matrix[`c_wrsw_num_ports][`c_n_pcks_to_send];
module main;
module main_7ports;
......@@ -93,8 +93,8 @@ module main;
xswcore_wrapper
DUT_xswcore_wrapper (
xswc_core_wrapper_7ports
DUT_xswc_core_wrapper(
.clk_i (clk),
.rst_n_i (rst_n),
//-------------------------------------------------------------------------------
......@@ -524,22 +524,22 @@ wait_cycles(80000);
///////// Monitoring allocation of pages /////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////
// always @(posedge clk) if(DUT.memory_management_unit.pg_addr_valid)
always @(posedge clk) if(DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_alloc & DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_done)
always @(posedge clk) if(DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.pg_alloc & DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.pg_done)
begin
int address;
int usecnt;
usecnt = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_usecnt;
usecnt = DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.pg_usecnt;
wait(DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_addr_valid);
wait(DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.pg_addr_valid);
address = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_addr_alloc;
address = DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.pg_addr_alloc;
pg_alloc_cnt[address][pg_alloc_cnt[address][0]+1]= usecnt;
pg_alloc_cnt[address][0]++;
alloc_table[address].usecnt[alloc_table[address].cnt] = usecnt;
alloc_table[address].port[alloc_table[address].cnt] = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.in_sel;
alloc_table[address].port[alloc_table[address].cnt] = DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.in_sel;
alloc_table[address].cnt++;
......@@ -551,11 +551,11 @@ wait_cycles(80000);
///////// Monitoring deallocation of pages /////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) if(DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.alloc_core.tmp_dbg_dealloc)
always @(posedge clk) if(DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.alloc_core.tmp_dbg_dealloc)
begin
int address;
address = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.alloc_core.tmp_page;
address = DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.alloc_core.tmp_page;
pg_dealloc_cnt[address][0]++;
......@@ -569,14 +569,14 @@ wait_cycles(80000);
///////// Monitoring freeing of pages /////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) if(DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_free & DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_done)
always @(posedge clk) if(DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.pg_free & DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.pg_done)
begin
int address;
int port_mask;
int port;
port = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.in_sel;
address = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_addr;
port = DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.in_sel;
address = DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.pg_addr;
port_mask = dealloc_table[address].port[dealloc_table[address].cnt ] ;
pg_dealloc_cnt[address][pg_dealloc_cnt[address][0] + 1]++;
......@@ -592,15 +592,15 @@ wait_cycles(80000);
///////// Monitoring setting of pages' usecnt /////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) if(DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_set_usecnt & DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_done)
always @(posedge clk) if(DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.pg_set_usecnt & DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.pg_done)
begin
int address;
address = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_addr;
address = DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.pg_addr;
pg_alloc_cnt[address][pg_alloc_cnt[address][0] + 1] = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_usecnt;
pg_alloc_cnt[address][pg_alloc_cnt[address][0] + 1] = DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.pg_usecnt;
alloc_table[address].usecnt[alloc_table[address].cnt - 1] = DUT_xswcore_wrapper.DUT_xswc_core_7_ports_wrapper.u_xswc_core.u_swc_core.memory_management_unit.pg_usecnt;;
alloc_table[address].usecnt[alloc_table[address].cnt - 1] = DUT_xswc_core_wrapper.DUT_swc_core_7ports_wrapper.U_xswc_core.memory_management_unit.pg_usecnt;;
end
......
testbench/swcore/xswc_core.v2.sv → testbench/swcore/swc_core_generic.sv
View file @ 31be1f04
......@@ -9,7 +9,7 @@
`include "wb_packet_source.svh"
`include "wb_packet_sink.svh"
`include "xswcore_wrapper.v2.svh"
`include "swc_core_wrapper_generic.svh"
`include "swc_param_defs.svh" // all swcore parameters here
`define DBG_ALLOC //if defined, the allocation debugging is active: we track the number of allocated
......@@ -33,7 +33,7 @@ int pg_dealloc_cnt[1024][2*`c_num_ports];
EthPacket swc_matrix[`c_num_ports][`c_n_pcks_to_send];
module main_v2;
module main_generic;
reg clk = 1'b0;
reg rst_n = 1'b0;
......@@ -72,7 +72,7 @@ module main_v2;
integer n_packets_to_send = `c_n_pcks_to_send;
integer dbg = 1;
xswcore_wrapper_v2
swc_core_wrapper_generic
DUT_xswcore_wrapper (
.clk_i (clk),
.rst_n_i (rst_n),
......
testbench/swcore/swc_core_single_port.sv deleted 100644 → 0
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testbench/swcore/xswc_core_7_ports_wrapper.vhd → testbench/swcore/swc_core_wrapper_7ports.vhd
View file @ 31be1f04
......@@ -2,11 +2,11 @@
-- Title : Switch Core V3
-- Project : WhiteRabbit switch
-------------------------------------------------------------------------------
-- File : xswc_core.vhd
-- File : swc_core_wrapper_7ports.vhd
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2012-01-15
-- Last update: 2012-01-15
-- Last update: 2012-02-07
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -38,6 +38,7 @@
-- Revisions :
-- Date Version Author Description
-- 2012-01-15 1.0 mlipinsk Created
-- 2012-02-07 1.1 mlipinsk changed name
-------------------------------------------------------------------------------
......@@ -50,7 +51,7 @@ use work.swc_swcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wrsw_shared_types_pkg.all;
entity xswc_core_7_ports_wrapper is
entity swc_core_wrapper_7ports is
generic
(
g_swc_num_ports : integer := 7;
......@@ -232,44 +233,10 @@ entity xswc_core_7_ports_wrapper is
rtu_prio_i : in std_logic_vector(g_swc_num_ports * g_swc_prio_width - 1 downto 0)
);
end xswc_core_7_ports_wrapper;
end swc_core_wrapper_7ports;
architecture rtl of xswc_core_7_ports_wrapper is
architecture rtl of swc_core_wrapper_7ports is
component xswc_core is
generic
(
g_num_ports : integer := g_swc_num_ports
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- Fabric I/F : input (comes from the Endpoint)
-------------------------------------------------------------------------------
snk_i : in t_wrf_sink_in_array(g_num_ports-1 downto 0);
snk_o : out t_wrf_sink_out_array(g_num_ports-1 downto 0);
-------------------------------------------------------------------------------
-- Fabric I/F : output (goes to the Endpoint)
-------------------------------------------------------------------------------
src_i : in t_wrf_source_in_array(g_num_ports-1 downto 0);
src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
-------------------------------------------------------------------------------
-- I/F with Routing Table Unit (RTU)
-------------------------------------------------------------------------------
rtu_rsp_i : in t_rtu_response_array(g_num_ports - 1 downto 0);
rtu_ack_o : out std_logic_vector(g_num_ports - 1 downto 0)
);
end component;
signal snk_i : t_wrf_sink_in_array(g_swc_num_ports-1 downto 0);
signal snk_o : t_wrf_sink_out_array(g_swc_num_ports-1 downto 0);
......@@ -282,6 +249,21 @@ end component;
begin
U_xswc_core: xswc_core
generic map(
g_mem_size => 65536,
g_page_size => 64,
g_prio_num => 8,
g_max_pck_size => 10 * 1024,
g_num_ports => 7,
g_data_width => 16,
g_ctrl_width => 4,
g_pck_pg_free_fifo_size => ((65536/64)/2) ,
g_input_block_cannot_accept_data => "drop_pck",
g_output_block_per_prio_fifo_size => 64,
g_packet_mem_multiply => 16,
g_input_block_fifo_size => (2 * 16),
g_input_block_fifo_full_in_advance => ((2 * 16) - 3)
)
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
......
testbench/swcore/xswcore_wrapper.v2.svh → testbench/swcore/swc_core_wrapper_generic.svh
View file @ 31be1f04
......@@ -5,7 +5,7 @@
`define array_assign(a, ah, al, b, bl) \
for (k=al; k<=ah; k=k+1) begin assign a[k] = b[bl+k-al]; end
module xswcore_wrapper_v2
module swc_core_wrapper_generic
(
clk_i,
rst_n_i,
......
testbench/swcore/swcore_wrapper.svh deleted 100644 → 0
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testbench/swcore/vish_stacktrace.vstf deleted 100644 → 0
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# Current time Mon Oct 18 18:05:56 2010
# ModelSim Stack Trace
# Program = vish
# Id = "6.6a"
# Version = "2010.03"
# Date = "Mar 19 2010"
# Platform = linux
# 0 0x08184ff0: 'treew_TriggerEventQ + 0x160' in '/opt/modeltech/modeltech/bin/../linux/vish'
# 1 0x0812ded3: 'name_ValueCancelPendingEvents + 0x1043' in '/opt/modeltech/modeltech/bin/../linux/vish'
# 2 0x083b138c: 'TclServiceIdle + 0x48' in '/opt/modeltech/modeltech/bin/../linux/vish'
# 3 0x083a3a99: 'Tcl_DoOneEvent + 0x1ad' in '/opt/modeltech/modeltech/bin/../linux/vish'
# 4 0x082cd87d: 'Tk_MainLoop + 0x19' in '/opt/modeltech/modeltech/bin/../linux/vish'
# 5 0x082d4a50: 'Tk_MainEx + 0x298' in '/opt/modeltech/modeltech/bin/../linux/vish'
# 6 0x0816b0e8: 'vish_inner_loop + 0x238' in '/opt/modeltech/modeltech/bin/../linux/vish'
# 7 0x0816bde2: 'main + 0x862' in '/opt/modeltech/modeltech/bin/../linux/vish'
# 8 0xb74ddbd1: '_libc_start_main + 0xe1' in '/lib/tls/i686/cmov/libc.so.6'
# 9 0x080bc3fc: 'start + 0x1c' in '/opt/modeltech/modeltech/bin/../linux/vish'
# End of Stack Trace
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