hdl: wrsw_swcore: minor bugfix in input block, added Makefile

48d0a0f2 · Tomasz Wlostowski · 318021ef · 48d0a0f2 · 48d0a0f2
Commit 48d0a0f2 authored Dec 07, 2010 by Tomasz Wlostowski
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Makefile Makefile +30 -0

swc_input_block.vhd swc_input_block.vhd +4 -3

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--- a/Makefile
+++ b/Makefile
+SRCS_VHDL = swc_swcore_pkg.vhd \
+swc_block_alloc.vhd \
+swc_core.vhd \
+swc_input_block.vhd \
+swc_lost_pck_dealloc.vhd \
+swc_multiport_linked_list.vhd \
+swc_multiport_page_allocator.vhd \
+swc_multiport_pck_pg_free_module.vhd \
+swc_ob_prio_queue.vhd \
+swc_output_block.vhd \
+swc_packet_mem.vhd \
+swc_packet_mem_read_pump.vhd \
+swc_packet_mem_write_pump.vhd \
+swc_page_alloc.vhd \
+swc_pck_pg_free_module.vhd \
+swc_pck_transfer_arbiter.vhd \
+swc_pck_transfer_input.vhd \
+swc_pck_transfer_output.vhd \
+swc_prio_encoder.vhd \
+swc_rr_arbiter.vhd 
+
+WORK = work
+
+#directories in which we should search for the VHDL/verilog source files
+VPATH =
+
+include ../../scripts/modules.mk
+
+
+
--- a/swc_input_block.vhd
+++ b/swc_input_block.vhd
@@ -6,7 +6,7 @@
 -- Author     : Maciej Lipinski
 -- Company    : CERN BE-Co-HT
 -- Created    : 2010-10-28
-- Last update: 2010-11-01
+-- Last update: 2010-12-07
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'87
 -------------------------------------------------------------------------------
@@ -396,7 +396,8 @@ begin --arch
 write_ctrl     <= fifo_data_out(c_swc_data_width + c_swc_ctrl_width - 1 downto c_swc_data_width) ;
 
 
- fifo_wr        <= tx_valid_i when (read_state = S_WRITE_FIFO) else '0';
+ fifo_wr        <= '1' when (read_state = S_WRITE_DUMMY_EOF)
+                   else tx_valid_i when (read_state = S_WRITE_FIFO) else '0';
 
 
 fifo_rd        <= ((not fifo_empty) and (not mpm_full_i)) when (write_state = S_WRITE_MPM  or 
@@ -1380,4 +1381,4 @@ end process;
  pta_pck_size_o         <= pta_pck_size;
  
  
-end syn; -- arch
\ No newline at end of file
+end syn; -- arch