[switch-optimization]: wrsw_rt_subsystem: adjust wb_spi parameters for the actual need of WR Switch

4f28fff4 · Grzegorz Daniluk · 9386e952 · a3e013e0 · 4f28fff4
Commit 4f28fff4 authored Sep 12, 2013 by Grzegorz Daniluk
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general-cores ip_cores/general-cores +1 -1

wrsw_rt_subsystem.vhd modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd +4 -2

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--- a/general-cores @ a3e013e0
+++ b/general-cores @ a3e013e0
-Subproject commit 8e0b776f4feb7f8244c9871c351b161a71efc65f
+Subproject commit a3e013e0ef817d24dcf00ed8bbe41bb3a5bb4d7f
--- a/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
+++ b/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
@@ -332,7 +332,10 @@ begin  -- rtl
  U_SPI_Master : xwb_spi
    generic map (
      g_interface_mode      => PIPELINED,
-      g_address_granularity => BYTE)
+      g_address_granularity => BYTE,
+      g_divider_len         => 8,
+      g_max_char_len        => 24,
+      g_num_slaves          => 1)
    port map (
      clk_sys_i            => clk_sys_i,
      rst_n_i              => rst_n_i,
@@ -340,7 +343,6 @@ begin  -- rtl
      slave_o              => cnx_master_in(c_SLAVE_SPI),
      desc_o               => open,
      pad_cs_o(0)          => pll_cs_n_o,
-      pad_cs_o(7 downto 1) => dummy(7 downto 1),
      pad_sclk_o           => pll_sck_o,
      pad_mosi_o           => pll_mosi_o,
      pad_miso_i           => pll_miso_i);