simulation models: simdrvs for CPU bus & NIC

5c47d2bb · Tomasz Wlostowski · aeb3c827 · 5c47d2bb · 5c47d2bb · 5c47d2bb
Commit 5c47d2bb authored Jan 19, 2012 by Tomasz Wlostowski
Showing with 736 additions and 0 deletions

nic_regs.vh sim/regs/nic_regs.vh +51 -0

simdrv_cpu_bus.sv sim/simdrv_cpu_bus.sv +119 -0

simdrv_wrsw_nic.svh sim/simdrv_wrsw_nic.svh +518 -0

softpll_regs_ng.vh sim/softpll_regs_ng.vh +48 -0

No files found.
--- a/sim/regs/nic_regs.vh
+++ b/sim/regs/nic_regs.vh
+`define ADDR_NIC_CR                    9'h0
+`define NIC_CR_RX_EN_OFFSET 0
+`define NIC_CR_RX_EN 32'h00000001
+`define NIC_CR_TX_EN_OFFSET 1
+`define NIC_CR_TX_EN 32'h00000002
+`define ADDR_NIC_SR                    9'h4
+`define NIC_SR_BNA_OFFSET 0
+`define NIC_SR_BNA 32'h00000001
+`define NIC_SR_REC_OFFSET 1
+`define NIC_SR_REC 32'h00000002
+`define NIC_SR_TX_DONE_OFFSET 2
+`define NIC_SR_TX_DONE 32'h00000004
+`define NIC_SR_TX_ERROR_OFFSET 3
+`define NIC_SR_TX_ERROR 32'h00000008
+`define NIC_SR_CUR_TX_DESC_OFFSET 8
+`define NIC_SR_CUR_TX_DESC 32'h00000700
+`define NIC_SR_CUR_RX_DESC_OFFSET 16
+`define NIC_SR_CUR_RX_DESC 32'h00070000
+`define ADDR_NIC_RESET                 9'h8
+`define ADDR_NIC_EIC_IDR               9'h20
+`define NIC_EIC_IDR_RCOMP_OFFSET 0
+`define NIC_EIC_IDR_RCOMP 32'h00000001
+`define NIC_EIC_IDR_TCOMP_OFFSET 1
+`define NIC_EIC_IDR_TCOMP 32'h00000002
+`define NIC_EIC_IDR_TXERR_OFFSET 2
+`define NIC_EIC_IDR_TXERR 32'h00000004
+`define ADDR_NIC_EIC_IER               9'h24
+`define NIC_EIC_IER_RCOMP_OFFSET 0
+`define NIC_EIC_IER_RCOMP 32'h00000001
+`define NIC_EIC_IER_TCOMP_OFFSET 1
+`define NIC_EIC_IER_TCOMP 32'h00000002
+`define NIC_EIC_IER_TXERR_OFFSET 2
+`define NIC_EIC_IER_TXERR 32'h00000004
+`define ADDR_NIC_EIC_IMR               9'h28
+`define NIC_EIC_IMR_RCOMP_OFFSET 0
+`define NIC_EIC_IMR_RCOMP 32'h00000001
+`define NIC_EIC_IMR_TCOMP_OFFSET 1
+`define NIC_EIC_IMR_TCOMP 32'h00000002
+`define NIC_EIC_IMR_TXERR_OFFSET 2
+`define NIC_EIC_IMR_TXERR 32'h00000004
+`define ADDR_NIC_EIC_ISR               9'h2c
+`define NIC_EIC_ISR_RCOMP_OFFSET 0
+`define NIC_EIC_ISR_RCOMP 32'h00000001
+`define NIC_EIC_ISR_TCOMP_OFFSET 1
+`define NIC_EIC_ISR_TCOMP 32'h00000002
+`define NIC_EIC_ISR_TXERR_OFFSET 2
+`define NIC_EIC_ISR_TXERR 32'h00000004
+`define BASE_NIC_DTX                   9'h80
+`define SIZE_NIC_DTX                   32'h20
+`define BASE_NIC_DRX                   9'h100
+`define SIZE_NIC_DRX                   32'h20
--- a/sim/simdrv_cpu_bus.sv
+++ b/sim/simdrv_cpu_bus.sv
+`include "simdrv_defs.svh"
+
+
+interface ICPUBus;
+   
+   
+/* I/O */  
+   logic[18:0] a = 0;
+   wire[31:0] d ;
+   logic cs 	 = 1;
+   logic rd 	 = 1;
+   logic wr 	 = 1;
+   wire nwait;
+
+   
+   bit data_hiz  = 1;
+   logic[31:0]  dr = 32'h0000000;
+   
+   assign d 	 =data_hiz ? 32'bz:dr;
+
+   parameter g_setup_delay  = 300ns;
+   parameter g_write_delay  = 300ns;
+   parameter g_hold_delay   = 300ns;
+   
+   
+   task write32(input [20:0] addr,
+		input [31:0] data);
+      
+      data_hiz  = 0;
+      cs        =0;
+      a         = addr >> 2;            
+      dr        = data;
+      
+      #(g_setup_delay) wr = 0;  
+      #(g_write_delay) 
+
+      if(!nwait) @(posedge nwait);
+      
+      wr = 1; 
+      #(g_hold_delay) wr = 1;
+      cs        =1;
+      data_hiz  = 1;
+   endtask // write32
+
+   task read32 (input [20:0] addr,
+		output [31:0] data);
+
+      integer i;
+      
+      data_hiz  = 1;            
+      a         = addr >> 2;            
+
+      cs        =0;
+      
+      #(g_setup_delay) rd = 0;  
+      #(g_write_delay) 
+      if(!nwait) @(posedge nwait);
+      
+      rd = 1;
+      data 	= d;
+      
+      #(g_hold_delay) rd = 1;
+      cs        =1;
+      
+      data_hiz  = 1;
+
+   endtask // read32
+
+   modport master
+     (
+      output a,
+      inout d,
+      output cs,
+      output rd,
+      output wr,
+      input nwait
+      );
+   
+class CAsyncCPUBusAccessor extends CBusAccessor;
+   
+    task writem(uint64_t addr[], uint64_t data[], input int size, ref int result);
+       int i;
+       
+       if(size != 4)
+	 $error("ICPUBus: we currently support only 32-bit transfers");
+       for(i=0; i<addr.size(); i++)
+	 write32(addr[i], data[i]);
+
+       result = 0;
+    endtask // writem
+   
+   task readm(uint64_t addr[], ref uint64_t data[], input int size, ref int result);
+      int i;
+      
+       if(size != 4)
+	 $error("ICPUBus: we currently support only 32-bit transfers");
+
+      
+      for(i=0; i<addr.size(); i++)
+	begin
+	   reg[31:0] rdata;
+	   read32(addr[i], rdata);
+	   data[i] = rdata;
+	end
+      result = 0;
+   endtask // readm
+   
+		
+endclass // CAsyncCPUBusAccessor
+
+   
+   function automatic CBusAccessor get_accessor();
+      CAsyncCPUBusAccessor acc = new;
+      return CBusAccessor'(acc);
+   endfunction // get_accessor
+   
+   
+endinterface // ICPUBus
+
--- a/sim/simdrv_wrsw_nic.svh
+++ b/sim/simdrv_wrsw_nic.svh
--- a/sim/softpll_regs_ng.vh
+++ b/sim/softpll_regs_ng.vh
+`define ADDR_SPLL_CSR                  6'h0
+`define SPLL_CSR_PER_SEL_OFFSET 0
+`define SPLL_CSR_PER_SEL 32'h0000003f
+`define SPLL_CSR_N_REF_OFFSET 8
+`define SPLL_CSR_N_REF 32'h00003f00
+`define SPLL_CSR_N_OUT_OFFSET 16
+`define SPLL_CSR_N_OUT 32'h00070000
+`define ADDR_SPLL_OCCR                 6'h4
+`define SPLL_OCCR_OUT_EN_OFFSET 0
+`define SPLL_OCCR_OUT_EN 32'h000000ff
+`define SPLL_OCCR_OUT_LOCK_OFFSET 8
+`define SPLL_OCCR_OUT_LOCK 32'h0000ff00
+`define ADDR_SPLL_RCER                 6'h8
+`define ADDR_SPLL_OCER                 6'hc
+`define ADDR_SPLL_PER_HPLL             6'h10
+`define SPLL_PER_HPLL_ERROR_OFFSET 0
+`define SPLL_PER_HPLL_ERROR 32'h0000ffff
+`define SPLL_PER_HPLL_VALID_OFFSET 16
+`define SPLL_PER_HPLL_VALID 32'h00010000
+`define ADDR_SPLL_DAC_HPLL             6'h14
+`define ADDR_SPLL_DAC_MAIN             6'h18
+`define SPLL_DAC_MAIN_VALUE_OFFSET 0
+`define SPLL_DAC_MAIN_VALUE 32'h0000ffff
+`define SPLL_DAC_MAIN_DAC_SEL_OFFSET 16
+`define SPLL_DAC_MAIN_DAC_SEL 32'h000f0000
+`define ADDR_SPLL_DEGLITCH_THR         6'h1c
+`define ADDR_SPLL_EIC_IDR              6'h20
+`define SPLL_EIC_IDR_TAG_OFFSET 0
+`define SPLL_EIC_IDR_TAG 32'h00000001
+`define ADDR_SPLL_EIC_IER              6'h24
+`define SPLL_EIC_IER_TAG_OFFSET 0
+`define SPLL_EIC_IER_TAG 32'h00000001
+`define ADDR_SPLL_EIC_IMR              6'h28
+`define SPLL_EIC_IMR_TAG_OFFSET 0
+`define SPLL_EIC_IMR_TAG 32'h00000001
+`define ADDR_SPLL_EIC_ISR              6'h2c
+`define SPLL_EIC_ISR_TAG_OFFSET 0
+`define SPLL_EIC_ISR_TAG 32'h00000001
+`define ADDR_SPLL_TRR_R0               6'h30
+`define SPLL_TRR_R0_VALUE_OFFSET 0
+`define SPLL_TRR_R0_VALUE 32'h00ffffff
+`define SPLL_TRR_R0_CHAN_ID_OFFSET 24
+`define SPLL_TRR_R0_CHAN_ID 32'h7f000000
+`define SPLL_TRR_R0_DISC_OFFSET 31
+`define SPLL_TRR_R0_DISC 32'h80000000
+`define ADDR_SPLL_TRR_CSR              6'h34
+`define SPLL_TRR_CSR_EMPTY_OFFSET 17
+`define SPLL_TRR_CSR_EMPTY 32'h00020000