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Commit 621cf0e4 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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HDL: wrsw_swcore: migrated RAMS/FIFOs to genrams

parent e4fb4e04
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Showing with 268 additions and 249 deletions
swc_input_block.vhd
View file @ 621cf0e4
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-10-28
-- Last update: 2010-12-07
-- Last update: 2011-03-16
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -63,7 +63,7 @@ use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
use work.platform_specific.all;
use work.genram_pkg.all;
entity swc_input_block is
......@@ -191,6 +191,7 @@ architecture syn of swc_input_block is
signal fifo_data_in : std_logic_vector(c_swc_data_width + c_swc_ctrl_width + 2 - 1 downto 0);
signal fifo_wr : std_logic;
signal fifo_clean : std_logic;
signal fifo_clear_n : std_logic;
signal fifo_rd : std_logic;
signal fifo_data_out : std_logic_vector(c_swc_data_width + c_swc_ctrl_width + 2 - 1 downto 0);
signal fifo_empty : std_logic;
......@@ -427,28 +428,30 @@ begin --arch
or fifo_full = '1') else '0';
fifo_full_in_advance <= '1'
when ((fifo_usedw > std_logic_vector(to_unsigned(c_swc_fifo_full_in_advance, c_swc_input_fifo_size_log2)))
when ((fifo_usedw > std_logic_vector(to_unsigned(c_swc_fifo_full_in_advance, c_swc_input_fifo_size_log2)))
or fifo_full = '1') else '0';
FIFO : generic_sync_fifo
fifo_clear_n <= not fifo_clean;
U_FIFO : generic_sync_fifo
generic map(
g_width => c_swc_data_width + c_swc_ctrl_width + 2,
g_depth => c_swc_input_fifo_size,
g_depth_log2 => c_swc_input_fifo_size_log2
g_data_width => c_swc_data_width + c_swc_ctrl_width + 2,
g_size => c_swc_input_fifo_size,
g_with_count => true
)
port map (
clk_i => clk_i,
clear_i => fifo_clean,
rst_n_i => fifo_clear_n,
wr_req_i => fifo_wr,
we_i => fifo_wr,
d_i => fifo_data_in,
rd_req_i => fifo_rd,
rd_i => fifo_rd,
q_o => fifo_data_out,
empty_o => fifo_empty,
full_o => fifo_full,
usedw_o => fifo_usedw
count_o => fifo_usedw
);
--==================================================================================================
......
swc_lost_pck_dealloc.vhd
View file @ 621cf0e4
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-15
-- Last update: 2010-11-15
-- Last update: 2011-03-15
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -48,7 +48,7 @@ use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
use work.platform_specific.all;
use work.genram_pkg.all;
entity swc_lost_pck_dealloc is
......@@ -107,18 +107,16 @@ architecture syn of swc_lost_pck_dealloc is
signal next_page : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal ll_read_req : std_logic;
signal mmu_force_free : std_logic;
signal ll_read_req : std_logic;
signal mmu_force_free : std_logic;
signal ones : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
begin -- syn
ones <= (others => '1');
fifo_clean <= not rst_n_i;
INPUT: process(clk_i, rst_n_i)
begin
......@@ -161,25 +159,24 @@ begin -- syn
end process;
FIFO: generic_sync_fifo
U_FIFO: generic_sync_fifo
generic map(
g_width => c_swc_page_addr_width,
g_depth => 16,
g_depth_log2 => 4
g_data_width => c_swc_page_addr_width,
g_size => 16
)
port map (
clk_i => clk_i,
clear_i => fifo_clean,
rst_n_i => rst_n_i,
wr_req_i => fifo_wr,
we_i => fifo_wr,
d_i => fifo_data_in,
rd_req_i => fifo_rd,
rd_i => fifo_rd,
q_o => fifo_data_out,
empty_o => fifo_empty,
full_o => fifo_full,
usedw_o => open
count_o => open
);
......
swc_page_alloc.vhd
View file @ 621cf0e4
This diff is collapsed.
swc_pck_pg_free_module.vhd
View file @ 621cf0e4
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-11-15
-- Last update: 2010-11-15
-- Last update: 2011-03-15
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -48,8 +48,7 @@ use ieee.numeric_std.all;
library work;
use work.swc_swcore_pkg.all;
use work.platform_specific.all;
use work.genram_pkg.all;
entity swc_pck_pg_free_module is
......@@ -93,7 +92,7 @@ architecture syn of swc_pck_pg_free_module is
S_READ_NEXT_PAGE_ADDR,
S_FREE_CURRENT_PAGE_ADDR,
S_FORCE_FREE_CURRENT_PAGE_ADDR
);
);
signal state : t_state;
......@@ -120,6 +119,7 @@ architecture syn of swc_pck_pg_free_module is
signal ones : std_logic_vector(c_swc_page_addr_width - 1 downto 0);
signal freeing_mode : std_logic_vector(1 downto 0);
signal fifo_clear_n : std_logic;
begin -- syn
......@@ -175,29 +175,29 @@ begin -- syn
end if;
end process;
FIFO: generic_sync_fifo
generic map(
g_width => c_swc_page_addr_width + 2,
g_depth => c_swc_freeing_fifo_size, --16,
g_depth_log2 => c_swc_freeing_fifo_log2 --4
)
port map (
clk_i => clk_i,
clear_i => fifo_clean,
wr_req_i => fifo_wr,
d_i => fifo_data_in,
rd_req_i => fifo_rd,
q_o => fifo_data_out,
empty_o => fifo_empty,
full_o => fifo_full,
usedw_o => open
);
fifo_clear_n <= not fifo_clean;
-- replaced by GenRams component: TW
U_FIFO: generic_sync_fifo
generic map (
g_data_width => c_swc_page_addr_width + 2,
g_size => c_swc_freeing_fifo_size
)
port map (
rst_n_i => fifo_clear_n,
clk_i => clk_i,
d_i => fifo_data_in,
we_i => fifo_wr,
q_o => fifo_data_out,
rd_i => fifo_rd,
empty_o => fifo_empty,
full_o => fifo_full,
almost_empty_o => open,
almost_full_o => open,
count_o => open);
fsm_force_free : process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
......
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