wrsw_rt_subsystem: reversed DDMTD with 125 MHz configuration to place all clocks…

wrsw_rt_subsystem: reversed DDMTD with 125 MHz configuration to place all clocks using global resources for 18-port FW

wrsw_rt_subsystem: reversed DDMTD with 125 MHz configuration to place all clocks…
wrsw_rt_subsystem: reversed DDMTD with 125 MHz configuration to place all clocks using global resources for 18-port FW
70f972c7 · Tomasz Wlostowski · 55705800 · 70f972c7
Commit 70f972c7 authored Jul 17, 2012 by Tomasz Wlostowski
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wrsw_rt_subsystem.vhd modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd +3 -1

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--- a/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
+++ b/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
@@ -83,6 +83,7 @@ architecture rtl of wrsw_rt_subsystem is
      g_with_debug_fifo      : boolean;
      g_with_ext_clock_input : boolean;
      g_with_undersampling   : boolean;
+      g_divide_input_by_2 : boolean;
      g_reverse_dmtds        : boolean;
      g_bb_ref_divider       : integer;
      g_bb_feedback_divider  : integer;
@@ -279,8 +280,9 @@ begin  -- rtl
      g_address_granularity  => BYTE,
      g_num_ref_inputs       => g_num_rx_clocks,
      g_num_outputs          => 1,
-      g_reverse_dmtds        => false,
+      g_reverse_dmtds        => true,
      g_with_ext_clock_input => true,
+      g_divide_input_by_2    => true,
      g_with_period_detector => false,
      g_with_undersampling   => false,
      g_with_debug_fifo      => true,