use new SoftPLL with rewritten Ext PLL

74be9eea · Grzegorz Daniluk · aca3b188 · 8b8334fc · de3d1970 · 74be9eea
Commit 74be9eea authored Jul 22, 2014 by Grzegorz Daniluk
12 changed files
--- a/general-cores @ 8b8334fc
+++ b/general-cores @ 8b8334fc
-Subproject commit 51180703c3ad6eb827446c2069daa2562b020c66
+Subproject commit 8b8334fcc156a7edb84eea6a920b5276f76a349d
--- a/wr-cores @ de3d1970
+++ b/wr-cores @ de3d1970
-Subproject commit 7efeb16415c92651efd544104a2d2a5eeac6d45d
+Subproject commit de3d1970e3904a034c9ee0471862242f1833ae65
--- a/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
+++ b/modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
@@ -53,6 +53,7 @@ entity wrsw_rt_subsystem is
    clk_dmtd_i : in std_logic;
    clk_rx_i   : in std_logic_vector(g_num_rx_clocks-1 downto 0);
    clk_ext_i  : in std_logic;
+		clk_ext_mul_i	:	in std_logic;

    rst_n_i : in  std_logic;
    rst_n_o : out std_logic;
@@ -106,7 +107,10 @@ entity wrsw_rt_subsystem is
    pll_sck_o     : out std_logic;
    pll_cs_n_o    : out std_logic;
    pll_sync_n_o  : out std_logic;
-    pll_reset_n_o : out std_logic
+    pll_reset_n_o : out std_logic;
+
+    -- Debug
+    spll_dbg_o  : out std_logic_vector(5 downto 0)
    );
 end wrsw_rt_subsystem;

@@ -121,6 +125,8 @@ architecture rtl of wrsw_rt_subsystem is
      g_with_ext_clock_input : boolean;
      g_divide_input_by_2 	 : boolean;
      g_reverse_dmtds        : boolean;
+    	g_ref_clock_rate			 : integer;
+    	g_ext_clock_rate			 : integer;
      g_interface_mode       : t_wishbone_interface_mode;
      g_address_granularity  : t_wishbone_address_granularity);
    port (
@@ -130,7 +136,9 @@ architecture rtl of wrsw_rt_subsystem is
      clk_fb_i        : in  std_logic_vector(g_num_outputs-1 downto 0);
      clk_dmtd_i      : in  std_logic;
      clk_ext_i       : in  std_logic;
-      sync_p_i        : in  std_logic;
+    	clk_ext_mul_i		: in std_logic;
+    	pps_csync_p1_i	: in std_logic;
+    	pps_ext_a_i			: in std_logic;
      dac_dmtd_data_o : out std_logic_vector(15 downto 0);
      dac_dmtd_load_o : out std_logic;
      dac_out_data_o  : out std_logic_vector(15 downto 0);
@@ -138,9 +146,10 @@ architecture rtl of wrsw_rt_subsystem is
      dac_out_load_o  : out std_logic;
      out_enable_i    : in  std_logic_vector(g_num_outputs-1 downto 0);
      out_locked_o    : out std_logic_vector(g_num_outputs-1 downto 0);
+    	out_status_o		: out std_logic_vector(4*g_num_outputs-1 downto 0);
      slave_i         : in  t_wishbone_slave_in;
      slave_o         : out t_wishbone_slave_out;
-      debug_o         : out std_logic_vector(3 downto 0);
+      debug_o         : out std_logic_vector(5 downto 0);
      dbg_fifo_irq_o  : out std_logic);
  end component;

@@ -225,6 +234,7 @@ architecture rtl of wrsw_rt_subsystem is
  signal dac_out_load, dac_dmtd_load : std_logic;

  signal clk_rx_vec : std_logic_vector(g_num_rx_clocks-1 downto 0);
+	signal pps_csync	:	std_logic;

  function f_pick (
    cond     : boolean;
@@ -316,15 +326,19 @@ begin  -- rtl
      g_reverse_dmtds        => true,
      g_with_ext_clock_input => true,
      g_divide_input_by_2    => false,
-      g_with_debug_fifo      => true)
+      g_with_debug_fifo      => true,
+			g_ref_clock_rate			 => 62500000,
+			g_ext_clock_rate			 => 10000000)
    port map (
      clk_sys_i       => clk_sys_i,
      rst_n_i         => rst_n_i,
      clk_ref_i       => clk_rx_vec,
      clk_fb_i(0)     => clk_ref_i,
-      clk_ext_i       => clk_ext_i,
-      sync_p_i        => pps_ext_i,
      clk_dmtd_i      => clk_dmtd_i,
+      clk_ext_i       => clk_ext_i,
+			clk_ext_mul_i		=> clk_ext_mul_i,
+			pps_csync_p1_i	=> pps_csync,
+      pps_ext_a_i     => pps_ext_i,
      dac_dmtd_data_o => dac_dmtd_data,
      dac_dmtd_load_o => dac_dmtd_load,
      dac_out_data_o  => dac_out_data,
@@ -334,8 +348,7 @@ begin  -- rtl
      out_locked_o    => open,
      slave_i         => cnx_master_out(c_SLAVE_SOFTPLL),
      slave_o         => cnx_master_in(c_SLAVE_SOFTPLL),
-      debug_o         => open);
-
+      debug_o         => spll_dbg_o);
  
  U_PPS_Gen : xwr_pps_gen
    generic map (
@@ -352,13 +365,15 @@ begin  -- rtl
      slave_i         => cnx_master_out(c_SLAVE_PPSGEN),
      slave_o         => cnx_master_in(c_SLAVE_PPSGEN),
      pps_in_i        => pps_ext_i,
-      pps_csync_o     => pps_csync_o,
+      pps_csync_o     => pps_csync,
      pps_out_o       => pps_ext_o,
      pps_valid_o     => pps_valid_o,
      tm_utc_o        => tm_utc_o,
      tm_cycles_o     => tm_cycles_o,
      tm_time_valid_o => tm_time_valid_o);

+	pps_csync_o	<= pps_csync;
+
  cpu_irq_vec(0)           <= cnx_master_in(2).int;
  cpu_irq_vec(31 downto 1) <= (others => '0');


--- a/platform/xilinx/Manifest.py
+++ b/platform/xilinx/Manifest.py
-files = ["pll200MhZ.vhd"];
+files = ["pll200MhZ.vhd", "ext_pll_10_to_100.vhd", "ext_pll_100_to_62m.vhd"];
--- a/platform/xilinx/ext_pll_100_to_62m.vhd
+++ b/platform/xilinx/ext_pll_100_to_62m.vhd
+-- file: ext_pll_100_to_62m.vhd
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1____62.500______0.000______50.0______144.481_____98.575
+--
+------------------------------------------------------------------------------
+-- "Input Clock   Freq (MHz)    Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity ext_pll_100_to_62m is
+port
+ (-- Clock in ports
+  clk_ext_100_i           : in     std_logic;
+  -- Clock out ports
+  clk_ext_mul_o          : out    std_logic;
+  -- Status and control signals
+  rst_a_i             : in     std_logic
+ );
+end ext_pll_100_to_62m;
+
+architecture xilinx of ext_pll_100_to_62m is
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of xilinx : architecture is "ext_pll_100_to_62m,clk_wiz_v3_6,{component_name=ext_pll_100_to_62m,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+  -- Input clock buffering / unused connectors
+  signal clkin1      : std_logic;
+  -- Output clock buffering / unused connectors
+  signal clkfbout         : std_logic;
+  signal clkfboutb_unused : std_logic;
+  signal clkout0          : std_logic;
+  signal clkout0b_unused  : std_logic;
+  signal clkout1_unused   : std_logic;
+  signal clkout1b_unused  : std_logic;
+  signal clkout2_unused   : std_logic;
+  signal clkout2b_unused  : std_logic;
+  signal clkout3_unused   : std_logic;
+  signal clkout3b_unused  : std_logic;
+  signal clkout4_unused   : std_logic;
+  signal clkout5_unused   : std_logic;
+  signal clkout6_unused   : std_logic;
+  -- Dynamic programming unused signals
+  signal do_unused        : std_logic_vector(15 downto 0);
+  signal drdy_unused      : std_logic;
+  -- Dynamic phase shift unused signals
+  signal psdone_unused    : std_logic;
+  -- Unused status signals
+  signal locked_unused    : std_logic;
+  signal clkfbstopped_unused : std_logic;
+  signal clkinstopped_unused : std_logic;
+begin
+
+
+  -- Input buffering
+  clkin1 <= clk_ext_100_i;
+
+
+  -- Clocking primitive
+  --------------------------------------
+  -- Instantiation of the MMCM primitive
+  --    * Unused inputs are tied off
+  --    * Unused outputs are labeled unused
+  mmcm_adv_inst : MMCM_ADV
+  generic map
+   (BANDWIDTH            => "OPTIMIZED",
+    CLKOUT4_CASCADE      => FALSE,
+    CLOCK_HOLD           => FALSE,
+    COMPENSATION         => "ZHOLD",
+    STARTUP_WAIT         => FALSE,
+    DIVCLK_DIVIDE        => 1,
+    CLKFBOUT_MULT_F      => 10.000,
+    CLKFBOUT_PHASE       => 0.000,
+    CLKFBOUT_USE_FINE_PS => FALSE,
+    CLKOUT0_DIVIDE_F     => 16.000,
+    CLKOUT0_PHASE        => 0.000,
+    CLKOUT0_DUTY_CYCLE   => 0.500,
+    CLKOUT0_USE_FINE_PS  => FALSE,
+    CLKIN1_PERIOD        => 10.000,
+    REF_JITTER1          => 0.010)
+  port map
+    -- Output clocks
+   (CLKFBOUT            => clkfbout,
+    CLKFBOUTB           => clkfboutb_unused,
+    CLKOUT0             => clkout0,
+    CLKOUT0B            => clkout0b_unused,
+    CLKOUT1             => clkout1_unused,
+    CLKOUT1B            => clkout1b_unused,
+    CLKOUT2             => clkout2_unused,
+    CLKOUT2B            => clkout2b_unused,
+    CLKOUT3             => clkout3_unused,
+    CLKOUT3B            => clkout3b_unused,
+    CLKOUT4             => clkout4_unused,
+    CLKOUT5             => clkout5_unused,
+    CLKOUT6             => clkout6_unused,
+    -- Input clock control
+    CLKFBIN             => clkfbout,
+    CLKIN1              => clkin1,
+    CLKIN2              => '0',
+    -- Tied to always select the primary input clock
+    CLKINSEL            => '1',
+    -- Ports for dynamic reconfiguration
+    DADDR               => (others => '0'),
+    DCLK                => '0',
+    DEN                 => '0',
+    DI                  => (others => '0'),
+    DO                  => do_unused,
+    DRDY                => drdy_unused,
+    DWE                 => '0',
+    -- Ports for dynamic phase shift
+    PSCLK               => '0',
+    PSEN                => '0',
+    PSINCDEC            => '0',
+    PSDONE              => psdone_unused,
+    -- Other control and status signals
+    LOCKED              => locked_unused,
+    CLKINSTOPPED        => clkinstopped_unused,
+    CLKFBSTOPPED        => clkfbstopped_unused,
+    PWRDWN              => '0',
+    RST                 => rst_a_i);
+
+  -- Output buffering
+  -------------------------------------
+
+
+  clkout1_buf : BUFG
+  port map
+   (O   => clk_ext_mul_o,
+    I   => clkout0);
+
+
+
+end xilinx;
--- a/platform/xilinx/ext_pll_10_to_100.vhd
+++ b/platform/xilinx/ext_pll_10_to_100.vhd
+-- file: ext_pll_10_to_100.vhd
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1___100.000______0.000______50.0______674.201____874.060
+--
+------------------------------------------------------------------------------
+-- "Input Clock   Freq (MHz)    Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary__________10.000____________0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity ext_pll_10_to_100 is
+port
+ (-- Clock in ports
+  clk_ext_i           : in     std_logic;
+  -- Clock out ports
+  clk_ext_100_o          : out    std_logic;
+  -- Status and control signals
+  rst_a_i             : in     std_logic
+ );
+end ext_pll_10_to_100;
+
+architecture xilinx of ext_pll_10_to_100 is
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of xilinx : architecture is "ext_pll_10_to_100,clk_wiz_v3_6,{component_name=ext_pll_10_to_100,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=100.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+  -- Input clock buffering / unused connectors
+  signal clkin1      : std_logic;
+  -- Output clock buffering / unused connectors
+  signal clkfbout         : std_logic;
+  signal clkfboutb_unused : std_logic;
+  signal clkout0          : std_logic;
+  signal clkout0b_unused  : std_logic;
+  signal clkout1_unused   : std_logic;
+  signal clkout1b_unused  : std_logic;
+  signal clkout2_unused   : std_logic;
+  signal clkout2b_unused  : std_logic;
+  signal clkout3_unused   : std_logic;
+  signal clkout3b_unused  : std_logic;
+  signal clkout4_unused   : std_logic;
+  signal clkout5_unused   : std_logic;
+  signal clkout6_unused   : std_logic;
+  -- Dynamic programming unused signals
+  signal do_unused        : std_logic_vector(15 downto 0);
+  signal drdy_unused      : std_logic;
+  -- Dynamic phase shift unused signals
+  signal psdone_unused    : std_logic;
+  -- Unused status signals
+  signal locked_unused    : std_logic;
+  signal clkfbstopped_unused : std_logic;
+  signal clkinstopped_unused : std_logic;
+begin
+
+
+  -- Input buffering
+  clkin1 <= clk_ext_i;
+
+
+  -- Clocking primitive
+  --------------------------------------
+  -- Instantiation of the MMCM primitive
+  --    * Unused inputs are tied off
+  --    * Unused outputs are labeled unused
+  mmcm_adv_inst : MMCM_ADV
+  generic map
+   (BANDWIDTH            => "OPTIMIZED",
+    CLKOUT4_CASCADE      => FALSE,
+    CLOCK_HOLD           => FALSE,
+    COMPENSATION         => "ZHOLD",
+    STARTUP_WAIT         => FALSE,
+    DIVCLK_DIVIDE        => 1,
+    CLKFBOUT_MULT_F      => 60.000,
+    CLKFBOUT_PHASE       => 0.000,
+    CLKFBOUT_USE_FINE_PS => FALSE,
+    CLKOUT0_DIVIDE_F     => 6.000,
+    CLKOUT0_PHASE        => 0.000,
+    CLKOUT0_DUTY_CYCLE   => 0.500,
+    CLKOUT0_USE_FINE_PS  => FALSE,
+    CLKIN1_PERIOD        => 100.0,
+    REF_JITTER1          => 0.010)
+  port map
+    -- Output clocks
+   (CLKFBOUT            => clkfbout,
+    CLKFBOUTB           => clkfboutb_unused,
+    CLKOUT0             => clkout0,
+    CLKOUT0B            => clkout0b_unused,
+    CLKOUT1             => clkout1_unused,
+    CLKOUT1B            => clkout1b_unused,
+    CLKOUT2             => clkout2_unused,
+    CLKOUT2B            => clkout2b_unused,
+    CLKOUT3             => clkout3_unused,
+    CLKOUT3B            => clkout3b_unused,
+    CLKOUT4             => clkout4_unused,
+    CLKOUT5             => clkout5_unused,
+    CLKOUT6             => clkout6_unused,
+    -- Input clock control
+    CLKFBIN             => clkfbout,
+    CLKIN1              => clkin1,
+    CLKIN2              => '0',
+    -- Tied to always select the primary input clock
+    CLKINSEL            => '1',
+    -- Ports for dynamic reconfiguration
+    DADDR               => (others => '0'),
+    DCLK                => '0',
+    DEN                 => '0',
+    DI                  => (others => '0'),
+    DO                  => do_unused,
+    DRDY                => drdy_unused,
+    DWE                 => '0',
+    -- Ports for dynamic phase shift
+    PSCLK               => '0',
+    PSEN                => '0',
+    PSINCDEC            => '0',
+    PSDONE              => psdone_unused,
+    -- Other control and status signals
+    LOCKED              => locked_unused,
+    CLKINSTOPPED        => clkinstopped_unused,
+    CLKFBSTOPPED        => clkfbstopped_unused,
+    PWRDWN              => '0',
+    RST                 => rst_a_i);
+
+  -- Output buffering
+  -------------------------------------
+
+
+  clkout1_buf : BUFG
+  port map
+   (O   => clk_ext_100_o,
+    I   => clkout0);
+
+
+
+end xilinx;
--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -81,6 +81,8 @@ entity scb_top_bare is
    -- for re-phasing the 10 MHz input as well as clocking the 
    clk_aux_i : in std_logic;

+		clk_ext_mul_i	:	in std_logic;
+
    -- Muxed system clock
    clk_sys_o : out std_logic;

@@ -170,7 +172,9 @@ entity scb_top_bare is
    ---------------------------------------------------------------------------

    mb_fan1_pwm_o : out std_logic;
-    mb_fan2_pwm_o : out std_logic
+    mb_fan2_pwm_o : out std_logic;
+
+    spll_dbg_o  : out std_logic_vector(5 downto 0)
    );
 end scb_top_bare;

@@ -536,6 +540,7 @@ begin
      clk_dmtd_i          => clk_dmtd_i,
      clk_rx_i            => clk_rx_vec,
      clk_ext_i           => pll_status_i,  -- FIXME: UGLY HACK
+			clk_ext_mul_i				=> clk_ext_mul_i,
      rst_n_i             => rst_n_sys,
      rst_n_o             => rst_n_periph,
      wb_i                => cnx_master_out(c_SLAVE_RT_SUBSYSTEM),
@@ -566,7 +571,8 @@ begin
      pll_sck_o     => pll_sck_o,
      pll_cs_n_o    => pll_cs_n_o,
      pll_sync_n_o  => pll_sync_n_o,
-      pll_reset_n_o => pll_reset_n_o);
+      pll_reset_n_o => pll_reset_n_o,
+      spll_dbg_o    => spll_dbg_o);

  U_IRQ_Controller : xwb_vic
    generic map (

--- a/top/bare_top/wrsw_top_pkg.vhd
+++ b/top/bare_top/wrsw_top_pkg.vhd
@@ -206,6 +206,7 @@ package wrsw_top_pkg is
      clk_dmtd_i          : in  std_logic;
      clk_rx_i            : in  std_logic_vector(g_num_rx_clocks-1 downto 0);
      clk_ext_i           : in  std_logic;
+      clk_ext_mul_i       : in  std_logic;
      rst_n_i             : in  std_logic;
      rst_n_o             : out std_logic;
      wb_i                : in  t_wishbone_slave_in;
@@ -232,7 +233,8 @@ package wrsw_top_pkg is
      pll_sck_o           : out std_logic;
      pll_cs_n_o          : out std_logic;
      pll_sync_n_o        : out std_logic;
-      pll_reset_n_o       : out std_logic);
+      pll_reset_n_o       : out std_logic;
+      spll_dbg_o          : out std_logic_vector(5 downto 0));
  end component;
  
  component chipscope_icon

--- a/top/scb_18ports/scb_top_synthesis.ucf
+++ b/top/scb_18ports/scb_top_synthesis.ucf
@@ -16,6 +16,13 @@ NET "fpga_clk_dmtd_n_i"  LOC=M22;
 NET "sensors_scl_b" LOC=G13;
 NET "sensors_sda_b" LOC=H14;

+NET "dbg_clk_ext_o" LOC=AM33;
+NET "spll_dbg_o<0>" LOC=AL33;
+NET "spll_dbg_o<1>" LOC=AE29;
+NET "spll_dbg_o<2>" LOC=AE28;
+NET "spll_dbg_o<3>" LOC=AM32;
+NET "spll_dbg_o<4>" LOC=AN32;
+NET "spll_dbg_o<5>" LOC=AP33;

 #EBI BUS
 #NET "cpu_clk_i" LOC="";
@@ -1528,4 +1535,4 @@ TIMESPEC TS_gen_phys_17__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[17].U_PHY/rx_

 #Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17
 TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
-TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY;
\ No newline at end of file
+TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY;
--- a/top/scb_18ports/scb_top_synthesis.vhd
+++ b/top/scb_18ports/scb_top_synthesis.vhd
@@ -180,7 +180,10 @@ entity scb_top_synthesis is
    sensors_sda_b: inout std_logic;

    mb_fan1_pwm_o : out std_logic;
-    mb_fan2_pwm_o : out std_logic
+    mb_fan2_pwm_o : out std_logic;
+
+		dbg_clk_ext_o	:	out std_logic;
+    spll_dbg_o    : out std_logic_vector(5 downto 0)
  );

 end scb_top_synthesis;
@@ -196,6 +199,20 @@ architecture Behavioral of scb_top_synthesis is
   );
  end component;

+  component ext_pll_10_to_100 is
+  port (
+    clk_ext_i           : in  std_logic;
+    clk_ext_100_o       : out std_logic;
+    rst_a_i             : in  std_logic);
+  end component;
+
+  component ext_pll_100_to_62m is
+  port(
+    clk_ext_100_i : in  std_logic;
+    clk_ext_mul_o : out std_logic;
+    rst_a_i       : in  std_logic);
+  end component;
+

  constant c_NUM_PHYS  : integer := 18;
  constant c_NUM_PORTS : integer := 18;
@@ -278,6 +295,9 @@ architecture Behavioral of scb_top_synthesis is
  attribute buffer_type of clk_aux  : signal is "BUFG";
  attribute buffer_type of clk_sys  : signal is "BUFG";

+	signal local_reset, ext_pll_reset : std_logic;
+	signal clk_ext, clk_ext_mul	:	 std_logic;
+  signal clk_ext_100 : std_logic;
  component scb_top_bare
    generic (
      g_num_ports       : integer;
@@ -296,6 +316,7 @@ architecture Behavioral of scb_top_synthesis is
      clk_ref_i           : in  std_logic;
      clk_dmtd_i          : in  std_logic;
      clk_aux_i           : in  std_logic;
+			clk_ext_mul_i				:	in	std_logic;
      clk_sys_o           : out std_logic;
      cpu_wb_i            : in  t_wishbone_slave_in;
      cpu_wb_o            : out t_wishbone_slave_out;
@@ -334,7 +355,8 @@ architecture Behavioral of scb_top_synthesis is
      i2c_sda_o       : out std_logic_vector(2 downto 0);
      i2c_sda_i       : in  std_logic_vector(2 downto 0) := "111";
      mb_fan1_pwm_o   : out std_logic;
-      mb_fan2_pwm_o   : out std_logic
+      mb_fan2_pwm_o   : out std_logic;
+      spll_dbg_o    : out std_logic_vector(5 downto 0)
      );
  end component;

@@ -508,6 +530,36 @@ begin
      CLKIN    => clk_25mhz);


+	-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
+	U_CLKEXT_BUF: IBUFG
+		port map (
+			I => pll_status_i,
+			O => clk_ext);
+
+  U_Ext_PLL1: ext_pll_10_to_100
+    port map(
+      clk_ext_i => clk_ext,
+      clk_ext_100_o => clk_ext_100,
+      rst_a_i   => ext_pll_reset);
+
+  U_Ext_PLL2: ext_pll_100_to_62m
+    port map(
+      clk_ext_100_i => clk_ext_100,
+      clk_ext_mul_o => clk_ext_mul,
+      rst_a_i => ext_pll_reset);
+
+	dbg_clk_ext_o	<= clk_ext_mul;
+
+	local_reset <= not sys_rst_n_i;
+	U_Extend_EXT_Reset: gc_extend_pulse
+		generic map (
+			g_width => 1000)
+		port map(
+			clk_i 		 => clk_sys,
+			rst_n_i 	 => sys_rst_n_i,
+			pulse_i		 => local_reset,
+			extended_o => ext_pll_reset);
+
  ------------------------------------------------    
  cmp_wb_cpu_bridge : wb_cpu_bridge
    --generic map(
@@ -661,6 +713,7 @@ begin
      clk_dmtd_i          => clk_dmtd,
      clk_sys_o           => clk_sys,
      clk_aux_i           => clk_aux,
+			clk_ext_mul_i				=> clk_ext_mul,
      cpu_wb_i            => top_master_out,
      cpu_wb_o            => top_master_in,
      cpu_irq_n_o         => cpu_irq_n_o,
@@ -672,7 +725,7 @@ begin
      dac_main_sync_n_o   => dac_main_sync_n_o,
      dac_main_sclk_o     => dac_main_sclk_o,
      dac_main_data_o     => dac_main_data_o,
-      pll_status_i        => pll_status_i,
+      pll_status_i        => clk_ext,
      pll_mosi_o          => pll_mosi_o,
      pll_miso_i          => pll_miso_i,
      pll_sck_o           => pll_sck_o,
@@ -697,7 +750,8 @@ begin
      i2c_sda_o       => i2c_sda_out,
      i2c_sda_i       => i2c_sda_in,
      mb_fan1_pwm_o   => mb_fan1_pwm_o,
-      mb_fan2_pwm_o   => mb_fan2_pwm_o);
+      mb_fan2_pwm_o   => mb_fan2_pwm_o,
+      spll_dbg_o      => spll_dbg_o);

  i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
  i2c_sda_in(1 downto 0) <= mbl_sda_b(1 downto 0);

--- a/top/scb_8ports/scb_top_synthesis.ucf
+++ b/top/scb_8ports/scb_top_synthesis.ucf
@@ -16,6 +16,13 @@ NET "fpga_clk_dmtd_n_i"  LOC=M22;
 NET "sensors_scl_b" LOC=G13;
 NET "sensors_sda_b" LOC=H14;

+NET "dbg_clk_ext_o" LOC=AM33;
+NET "spll_dbg_o<0>" LOC=AL33;
+NET "spll_dbg_o<1>" LOC=AE29;
+NET "spll_dbg_o<2>" LOC=AE28;
+NET "spll_dbg_o<3>" LOC=AM32;
+NET "spll_dbg_o<4>" LOC=AN32;
+NET "spll_dbg_o<5>" LOC=AP33;

 #EBI BUS
 #NET "cpu_clk_i" LOC="";

--- a/top/scb_8ports/scb_top_synthesis.vhd
+++ b/top/scb_8ports/scb_top_synthesis.vhd
@@ -185,14 +185,16 @@ entity scb_top_synthesis is
    sensors_sda_b: inout std_logic;

    mb_fan1_pwm_o : out std_logic;
-    mb_fan2_pwm_o : out std_logic
+    mb_fan2_pwm_o : out std_logic;
+
+		dbg_clk_ext_o	:	out std_logic;
+    spll_dbg_o    : out std_logic_vector(5 downto 0)
  );

 end scb_top_synthesis;

 architecture Behavioral of scb_top_synthesis is

-
  component swcore_pll is
   port
   (-- Clock in ports
@@ -202,6 +204,19 @@ architecture Behavioral of scb_top_synthesis is
   );
  end component;

+  component ext_pll_10_to_100 is
+  port (
+    clk_ext_i           : in  std_logic;
+    clk_ext_100_o       : out std_logic;
+    rst_a_i             : in  std_logic);
+  end component;
+
+  component ext_pll_100_to_62m is
+  port(
+    clk_ext_100_i : in  std_logic;
+    clk_ext_mul_o : out std_logic;
+    rst_a_i       : in  std_logic);
+  end component;


  constant c_NUM_PHYS  : integer := 8;
@@ -281,6 +296,10 @@ architecture Behavioral of scb_top_synthesis is
  attribute buffer_type of clk_aux  : signal is "BUFG";
  attribute buffer_type of clk_sys  : signal is "BUFG";

+	signal local_reset, ext_pll_reset : std_logic;
+	signal clk_ext, clk_ext_mul	:	 std_logic;
+  signal clk_ext_100 : std_logic;
+
  component scb_top_bare
    generic (
      g_num_ports       : integer;
@@ -299,6 +318,7 @@ architecture Behavioral of scb_top_synthesis is
      clk_ref_i           : in  std_logic;
      clk_dmtd_i          : in  std_logic;
      clk_aux_i           : in  std_logic;
+			clk_ext_mul_i				:	in	std_logic;
      clk_sys_o           : out std_logic;
      cpu_wb_i            : in  t_wishbone_slave_in;
      cpu_wb_o            : out t_wishbone_slave_out;
@@ -337,7 +357,8 @@ architecture Behavioral of scb_top_synthesis is
      i2c_sda_o       : out std_logic_vector(2 downto 0);
      i2c_sda_i       : in  std_logic_vector(2 downto 0) := "111";
      mb_fan1_pwm_o : out std_logic;
-      mb_fan2_pwm_o : out std_logic
+      mb_fan2_pwm_o : out std_logic;
+      spll_dbg_o    : out std_logic_vector(5 downto 0)
      );
  end component;

@@ -511,6 +532,36 @@ begin
      CLKIN    => clk_25mhz);


+	-- Make 62.5MHz from 10MHz for locking ext clock in new SoftPLL
+	U_CLKEXT_BUF: IBUFG
+		port map (
+			I => pll_status_i,
+			O => clk_ext);
+
+  U_Ext_PLL1: ext_pll_10_to_100
+    port map(
+      clk_ext_i => clk_ext,
+      clk_ext_100_o => clk_ext_100,
+      rst_a_i   => ext_pll_reset);
+
+  U_Ext_PLL2: ext_pll_100_to_62m
+    port map(
+      clk_ext_100_i => clk_ext_100,
+      clk_ext_mul_o => clk_ext_mul,
+      rst_a_i => ext_pll_reset);
+
+	dbg_clk_ext_o	<= clk_ext_mul;
+
+	local_reset <= not sys_rst_n_i;
+	U_Extend_EXT_Reset: gc_extend_pulse
+		generic map (
+			g_width => 1000)
+		port map(
+			clk_i 		 => clk_sys,
+			rst_n_i 	 => sys_rst_n_i,
+			pulse_i		 => local_reset,
+			extended_o => ext_pll_reset);
+
  ------------------------------------------------    
  cmp_wb_cpu_bridge : wb_cpu_bridge
    --generic map(
@@ -665,6 +716,7 @@ begin
      clk_dmtd_i          => clk_dmtd,
      clk_sys_o           => clk_sys,
      clk_aux_i           => clk_aux,
+			clk_ext_mul_i				=> clk_ext_mul,
      cpu_wb_i            => top_master_out,
      cpu_wb_o            => top_master_in,
      cpu_irq_n_o         => cpu_irq_n_o,
@@ -676,7 +728,7 @@ begin
      dac_main_sync_n_o   => dac_main_sync_n_o,
      dac_main_sclk_o     => dac_main_sclk_o,
      dac_main_data_o     => dac_main_data_o,
-      pll_status_i        => pll_status_i,
+      pll_status_i        => clk_ext,
      pll_mosi_o          => pll_mosi_o,
      pll_miso_i          => pll_miso_i,
      pll_sck_o           => pll_sck_o,
@@ -701,7 +753,8 @@ begin
      i2c_sda_o       => i2c_sda_out,
      i2c_sda_i       => i2c_sda_in,
      mb_fan1_pwm_o   => mb_fan1_pwm_o,
-      mb_fan2_pwm_o   => mb_fan2_pwm_o);
+      mb_fan2_pwm_o   => mb_fan2_pwm_o,
+      spll_dbg_o      => spll_dbg_o);

  i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
  i2c_sda_in(1 downto 0) <= mbl_sda_b(1 downto 0);