Skip to content

W
White Rabbit Switch - Gateware
Commit 76196c22 authored by Mario Lizana's avatar Mario Lizana
Browse files
Options

The FPGA REF CLK is now connected to the output 5 of the AD9516 (instead of 8)

parent 0e9ae9d4
Hide whitespace changes
Inline Side-by-side
Showing with 7 additions and 3 deletions
.gitmodules
View file @ 76196c22
...@@ -3,4 +3,4 @@ ...@@ -3,4 +3,4 @@
url = https://ohwr.org/project/general-cores.git url = https://ohwr.org/project/general-cores.git
[submodule "ip_cores/wr-cores"] [submodule "ip_cores/wr-cores"]
path = ip_cores/wr-cores path = ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git url = https://bitbucket.org/sevensols/wr-cores.git
top/scb_18ports/scb_top_synthesis.ucf
View file @ 76196c22
...@@ -5,8 +5,12 @@ NET "fpga_clk_25mhz_p_i" LOC=K24; ...@@ -5,8 +5,12 @@ NET "fpga_clk_25mhz_p_i" LOC=K24;
NET "fpga_clk_25mhz_n_i" LOC=K23; NET "fpga_clk_25mhz_n_i" LOC=K23;
# REF_CLK from AD9516 OUT8 # REF_CLK from AD9516 OUT8
NET "fpga_clk_ref_p_i" LOC=J9; #NET "fpga_clk_ref_p_i" LOC=J9;
NET "fpga_clk_ref_n_i" LOC=H9; #NET "fpga_clk_ref_n_i" LOC=H9;
#Changes made so the output 8 of the ad9516 is now free.
#The REF CLK of the FPGA is now connected to the output 5 of the AD9516.
NET "fpga_clk_ref_p_i" LOC=F21;
NET "fpga_clk_ref_n_i" LOC=G20;
# FPGA clk dmtd changes frequency (125 MHz now) and is not differential anymore. # FPGA clk dmtd changes frequency (125 MHz now) and is not differential anymore.
# Comes from VCXO controlled by DMTD_DAC_OUT (dac_helper_data_o) # Comes from VCXO controlled by DMTD_DAC_OUT (dac_helper_data_o)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment