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White Rabbit Switch - Gateware
Commit 799e2c1a authored by Maciej Lipinski's avatar Maciej Lipinski
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RTU and TRU: minor changes

parent ec64c716
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Showing with 8 additions and 7 deletions
modules/wrsw_rtu/xwrsw_rtu_new.vhd
View file @ 799e2c1a
...@@ -648,7 +648,7 @@ begin ...@@ -648,7 +648,7 @@ begin
regs_towb.rx_ff_mac_r1_id_i <= std_logic_vector(to_unsigned(c_ff_single_macs_number, 8)); regs_towb.rx_ff_mac_r1_id_i <= std_logic_vector(to_unsigned(c_ff_single_macs_number, 8));
regs_towb.rx_ff_mac_r1_hi_id_i <= std_logic_vector(to_unsigned(c_ff_range_macs_number, 16)); regs_towb.rx_ff_mac_r1_hi_id_i <= std_logic_vector(to_unsigned(c_ff_range_macs_number, 16));
regs_towb.gcr_rtu_version_i <= x"4"; regs_towb.gcr_rtu_version_i <= x"5";
-- RTU Extension index-access configration regiters for Fast Forward MACs -- RTU Extension index-access configration regiters for Fast Forward MACs
p_rx_registers : process(clk_sys_i) p_rx_registers : process(clk_sys_i)
......
modules/wrsw_tru/xwrsw_tru.vhd
View file @ 799e2c1a
...@@ -259,8 +259,9 @@ begin --rtl ...@@ -259,8 +259,9 @@ begin --rtl
s_endpoints.inject_ready(i) <= s_endpoint_array(i).inject_ready; s_endpoints.inject_ready(i) <= s_endpoint_array(i).inject_ready;
end generate G_ENDP_CONX; end generate G_ENDP_CONX;
s_endpoints.status(s_endpoints.status'length-1 downto g_num_ports) <= (others =>'0'); s_endpoints.status(s_endpoints.status'length-1 downto g_num_ports) <= (others =>'0');
s_endpoints.stableUp(s_endpoints.stableUp'length-1 downto g_num_ports) <= (others =>'0'); s_endpoints.stableUp(s_endpoints.stableUp'length-1 downto g_num_ports) <= (others =>'0');
s_endpoints.inject_ready(s_endpoints.inject_ready'length-1 downto g_num_ports) <= (others =>'0');
G_FRAME_MASK: for i in 0 to g_pclass_number-1 generate G_FRAME_MASK: for i in 0 to g_pclass_number-1 generate
s_endpoints.rxFrameMask(i) <= f_rxFrameMaskInv(s_endpoint_array,i,g_num_ports); s_endpoints.rxFrameMask(i) <= f_rxFrameMaskInv(s_endpoint_array,i,g_num_ports);
......
testbench/scb_top/main.sv
View file @ 799e2c1a
...@@ -632,7 +632,7 @@ module main; ...@@ -632,7 +632,7 @@ module main;
* detecting different classes of incoming packets using pFilter * detecting different classes of incoming packets using pFilter
* *
**/ **/
/* ///*
initial begin initial begin
portUnderTest = 18'b000000000000010001; portUnderTest = 18'b000000000000010001;
g_tru_enable = 0; g_tru_enable = 0;
...@@ -675,7 +675,7 @@ module main; ...@@ -675,7 +675,7 @@ module main;
mc.logic2(27, 1, PFilterMicrocode::AND, 5); mc.logic2(27, 1, PFilterMicrocode::AND, 5);
end end
*/ //*/
/** *************************** test scenario 21 ********************** **/ /** *************************** test scenario 21 ********************** **/
/** *************************** (IMPORTANT) ********************** **/ /** *************************** (IMPORTANT) ********************** **/
/* /*
...@@ -943,7 +943,7 @@ module main; ...@@ -943,7 +943,7 @@ module main;
* - sending PAUSE frames * - sending PAUSE frames
* - making some strange configuration of TATSU * - making some strange configuration of TATSU
**/ **/
// /* /*
initial begin initial begin
portUnderTest = 18'b000000000000000111; portUnderTest = 18'b000000000000000111;
g_active_port = 0; g_active_port = 0;
...@@ -962,7 +962,7 @@ module main; ...@@ -962,7 +962,7 @@ module main;
g_traffic_shaper_scenario = 1; g_traffic_shaper_scenario = 1;
end end
//*/ */
/** *************************** test scenario 29 ************************************* **/ /** *************************** test scenario 29 ************************************* **/
/* /*
* *
......
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