swcore[new mpm]: modified (thoroughly) input_block (+ other necessary changes)…

swcore[new mpm]: modified (thoroughly) input_block (+ other necessary changes) to work with the new mpm (asynch by Tom)

swcore[new mpm]: modified (thoroughly) input_block (+ other necessary changes)…
swcore[new mpm]: modified (thoroughly) input_block (+ other necessary changes) to work with the new mpm (asynch by Tom)
7d015b17 · Maciej Lipinski · ec2662e2 · 7d015b17 · 7d015b17 · 7d015b17
Commit 7d015b17 authored Feb 15, 2012 by Maciej Lipinski
14 changed files
--- a/modules/wrsw_swcore/Manifest.py
+++ b/modules/wrsw_swcore/Manifest.py
@@ -30,4 +30,5 @@ files = [
 "xswc_output_block.vhd",
 "xswc_input_block.vhd",
 "../wrsw_shared_types_pkg.vhd",
-]
\ No newline at end of file
+]
+modules = modules = {"local": ["mpm"]}
\ No newline at end of file
--- a/modules/wrsw_swcore/mpm/Manifest.py
+++ b/modules/wrsw_swcore/mpm/Manifest.py
@@ -9,6 +9,7 @@ files = ["mpm_async_grow_fifo.vhd",
         "mpm_read_path.vhd",
         "mpm_async_fifo.vhd",
         "mpm_rpath_io_block.vhd",
-         "mpm_rpath_core_block.vhd"]
+         "mpm_rpath_core_block.vhd",
+         "mpm_pkg.vhd"]


--- a/modules/wrsw_swcore/mpm/mpm_pkg.vhd
+++ b/modules/wrsw_swcore/mpm/mpm_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : Multiport Memory Package
+-- Project    : WhiteRabbit switch
+-------------------------------------------------------------------------------
+-- File       : mpm_pkg.vhd
+-- Author     : Maciej Lipinski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-02-14
+-- Last update: 2012-02-14
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: 
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2010 Tomasz Wlostowski, Maciej Lipinski / CERN
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author   Description
+-- 2012-02-14  1.0      mlipinsk created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.math_real.CEIL;
+use ieee.math_real.log2;
+
+package mpm_pkg is
+
+  component mpm_top is
+  generic (
+    g_data_width           : integer := 18;
+    g_ratio                : integer := 2;
+    g_page_size            : integer := 64;
+    g_num_pages            : integer := 2048;
+    g_num_ports            : integer := 8;
+    g_fifo_size            : integer := 4;
+    g_page_addr_width      : integer := 11;
+    g_partial_select_width : integer := 1;
+    g_max_packet_size      : integer := 10000
+    );
+
+  port(
+    clk_io_i   : in std_logic;
+    clk_core_i : in std_logic;
+    rst_n_i    : in std_logic;
+
+    wport_d_i       : in  std_logic_vector (g_num_ports * g_data_width -1 downto 0);
+    wport_dvalid_i  : in  std_logic_vector (g_num_ports-1 downto 0);
+    wport_dlast_i   : in  std_logic_vector (g_num_ports-1 downto 0);
+    wport_pg_addr_i : in  std_logic_vector (g_num_ports * g_page_addr_width -1 downto 0);
+    wport_pg_req_o  : out std_logic_vector(g_num_ports -1 downto 0);
+    wport_dreq_o    : out std_logic_vector (g_num_ports-1 downto 0);
+
+    rport_d_o        : out std_logic_vector (g_num_ports * g_data_width -1 downto 0);
+    rport_dvalid_o   : out std_logic_vector (g_num_ports-1 downto 0);
+    rport_dlast_o    : out std_logic_vector (g_num_ports-1 downto 0);
+    rport_dsel_o     : out std_logic_vector (g_num_ports * g_partial_select_width -1 downto 0);
+    rport_dreq_i     : in  std_logic_vector (g_num_ports-1 downto 0);
+    rport_abort_i    : in  std_logic_vector (g_num_ports-1 downto 0);
+    rport_pg_addr_i  : in  std_logic_vector (g_num_ports * g_page_addr_width -1 downto 0);
+    rport_pg_valid_i : in  std_logic_vector (g_num_ports-1 downto 0);
+    rport_pg_req_o   : out std_logic_vector (g_num_ports-1 downto 0);
+
+    ll_addr_o : out std_logic_vector(g_page_addr_width-1 downto 0);
+    ll_data_i : in  std_logic_vector(g_page_addr_width+1 downto 0)
+    );
+   end component; 
+
+end mpm_pkg;
+
+package body mpm_pkg is
+
+end mpm_pkg;
--- a/modules/wrsw_swcore/swc_core.vhd
+++ b/modules/wrsw_swcore/swc_core.vhd
@@ -54,54 +54,62 @@ use work.wrsw_shared_types_pkg.all;

 entity swc_core is
  generic( 
-    g_mem_size                         : integer ;--:= c_swc_packet_mem_size
-    g_page_size                        : integer ;--:= c_swc_page_size
    g_prio_num                         : integer ;--:= c_swc_output_prio_num;
    g_max_pck_size                     : integer ;--:= 2^c_swc_max_pck_size
    g_num_ports                        : integer ;--:= c_swc_num_ports
-    g_data_width                       : integer ;--:= c_swc_data_width
-    g_ctrl_width                       : integer ; --:= c_swc_ctrl_width
    g_pck_pg_free_fifo_size            : integer ; --:= c_swc_freeing_fifo_size (in pck_pg_free_module.vhd)
    g_input_block_cannot_accept_data   : string  ;--:= "drop_pck"; --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
    g_output_block_per_prio_fifo_size  : integer ; --:= c_swc_output_fifo_size    (xswc_output_block)
-
+    -- new
+    g_wb_data_width                    : integer ;
+    g_wb_addr_width                    : integer ;
+    g_wb_sel_width                     : integer ;
+    g_mpm_mem_size                     : integer ;
+    g_mpm_page_size                    : integer ;
+    g_mpm_ratio                        : integer ;
+    g_mpm_fifo_size                    : integer ;
    -- probably useless with new memory
+    g_ctrl_width                       : integer ; --:= c_swc_ctrl_width
+    -- g_data_width                       : integer ;--:= c_swc_data_width
+    -- g_mem_size                         : integer ;--:= c_swc_packet_mem_size
+    -- g_page_size                        : integer ;--:= c_swc_page_size   
    g_packet_mem_multiply              : integer ;--:= c_swc_packet_mem_multiply (xswc_input_block, )
    g_input_block_fifo_size            : integer ;--:= c_swc_input_fifo_size     (xswc_input_block)
    g_input_block_fifo_full_in_advance : integer --:=c_swc_fifo_full_in_advance (xswc_input_block)

    );
  port (
-    clk_i   : in std_logic;
-    rst_n_i : in std_logic;
+    clk_i          : in std_logic;
+    clk_mpm_core_i : in std_logic;
+    rst_n_i        : in std_logic;

 -------------------------------------------------------------------------------
 -- pWB  : input (comes from the Endpoint)
 -------------------------------------------------------------------------------

-    snk_dat_i   : in  std_logic_vector(g_data_width*g_num_ports-1 downto 0);
-    snk_adr_i   : in  std_logic_vector(           2*g_num_ports-1 downto 0);
-    snk_sel_i   : in  std_logic_vector(           2*g_num_ports-1 downto 0);
-    snk_cyc_i   : in  std_logic_vector(             g_num_ports-1 downto 0);
-    snk_stb_i   : in  std_logic_vector(             g_num_ports-1 downto 0);
-    snk_we_i    : in  std_logic_vector(             g_num_ports-1 downto 0);
-    snk_stall_o : out std_logic_vector(             g_num_ports-1 downto 0);
-    snk_ack_o   : out std_logic_vector(             g_num_ports-1 downto 0);
-    snk_err_o   : out std_logic_vector(             g_num_ports-1 downto 0);
-    snk_rty_o   : out std_logic_vector(             g_num_ports-1 downto 0);
+    snk_dat_i   : in  std_logic_vector(g_wb_data_width*g_num_ports-1 downto 0);
+    snk_adr_i   : in  std_logic_vector(g_wb_addr_width*g_num_ports-1 downto 0);
+    snk_sel_i   : in  std_logic_vector(g_wb_sel_width *g_num_ports-1 downto 0);
+    snk_cyc_i   : in  std_logic_vector(                g_num_ports-1 downto 0);
+    snk_stb_i   : in  std_logic_vector(                g_num_ports-1 downto 0);
+    snk_we_i    : in  std_logic_vector(                g_num_ports-1 downto 0);
+    snk_stall_o : out std_logic_vector(                g_num_ports-1 downto 0);
+    snk_ack_o   : out std_logic_vector(                g_num_ports-1 downto 0);
+    snk_err_o   : out std_logic_vector(                g_num_ports-1 downto 0);
+    snk_rty_o   : out std_logic_vector(                g_num_ports-1 downto 0);
   
 -------------------------------------------------------------------------------
 -- pWB : output (goes to the Endpoint)
 -------------------------------------------------------------------------------  
-    src_dat_o   : out std_logic_vector(g_data_width*g_num_ports-1  downto 0);
-    src_adr_o   : out std_logic_vector(           2*g_num_ports-1 downto 0);
-    src_sel_o   : out std_logic_vector(           2*g_num_ports-1 downto 0);
-    src_cyc_o   : out std_logic_vector(             g_num_ports-1 downto 0);
-    src_stb_o   : out std_logic_vector(             g_num_ports-1 downto 0);
-    src_we_o    : out std_logic_vector(             g_num_ports-1 downto 0);
-    src_stall_i : in  std_logic_vector(             g_num_ports-1 downto 0);
-    src_ack_i   : in  std_logic_vector(             g_num_ports-1 downto 0);
-    src_err_i   : in  std_logic_vector(             g_num_ports-1 downto 0);
+    src_dat_o   : out std_logic_vector(g_wb_data_width*g_num_ports-1  downto 0);
+    src_adr_o   : out std_logic_vector(g_wb_addr_width*g_num_ports-1 downto 0);
+    src_sel_o   : out std_logic_vector(g_wb_sel_width *g_num_ports-1 downto 0);
+    src_cyc_o   : out std_logic_vector(                g_num_ports-1 downto 0);
+    src_stb_o   : out std_logic_vector(                g_num_ports-1 downto 0);
+    src_we_o    : out std_logic_vector(                g_num_ports-1 downto 0);
+    src_stall_i : in  std_logic_vector(                g_num_ports-1 downto 0);
+    src_ack_i   : in  std_logic_vector(                g_num_ports-1 downto 0);
+    src_err_i   : in  std_logic_vector(                g_num_ports-1 downto 0);

 -------------------------------------------------------------------------------
 -- I/F with Routing Table Unit (RTU)
@@ -131,39 +139,47 @@ architecture rtl of swc_core is

  xswcore: xswc_core
    generic map( 
-      g_mem_size                         => g_mem_size,
-      g_page_size                        => g_page_size,
      g_prio_num                         => g_prio_num,
      g_max_pck_size                     => g_max_pck_size,
      g_num_ports                        => g_num_ports,
-      g_data_width                       => g_data_width,
-      g_ctrl_width                       => g_ctrl_width,
      g_pck_pg_free_fifo_size            => g_pck_pg_free_fifo_size,
      g_input_block_cannot_accept_data   => g_input_block_cannot_accept_data,
      g_output_block_per_prio_fifo_size  => g_output_block_per_prio_fifo_size,
+
+      g_wb_data_width                    => g_wb_data_width,
+      g_wb_addr_width                    => g_wb_addr_width,
+      g_wb_sel_width                     => g_wb_sel_width,
+
+      g_mpm_mem_size                     => g_mpm_mem_size,
+      g_mpm_page_size                    => g_mpm_page_size,
+      g_mpm_ratio                        => g_mpm_ratio,
+      g_mpm_fifo_size                    => g_mpm_fifo_size,
+
+      g_ctrl_width                       => g_ctrl_width,
      g_packet_mem_multiply              => g_packet_mem_multiply,
      g_input_block_fifo_size            => g_input_block_fifo_size,
      g_input_block_fifo_full_in_advance => g_input_block_fifo_full_in_advance
      )
    port map(
-      clk_i      => clk_i,
-      rst_n_i    => rst_n_i,
+      clk_i          => clk_i,
+      clk_mpm_core_i => clk_mpm_core_i,
+      rst_n_i        => rst_n_i,

-      snk_i      => snk_i,
-      snk_o      => snk_o,
+      snk_i          => snk_i,
+      snk_o          => snk_o,
  
-      src_i      => src_i,
-      src_o      => src_o,
+      src_i          => src_i,
+      src_o          => src_o,
      
-      rtu_rsp_i  => rtu_rsp_i,
-      rtu_ack_o  => rtu_rsp_ack_o
+      rtu_rsp_i      => rtu_rsp_i,
+      rtu_ack_o      => rtu_rsp_ack_o
      );


    vectorize : for i in 0 to g_num_ports-1 generate
-      snk_i(i).dat  <= snk_dat_i((i+1)*16 - 1 downto i*16);   
-      snk_i(i).adr  <= snk_adr_i((i+1)*2  - 1 downto i*2);   
-      snk_i(i).sel  <= snk_sel_i((i+1)*2  - 1 downto i*2);   
+      snk_i(i).dat  <= snk_dat_i((i+1)*g_wb_data_width - 1 downto i*g_wb_data_width);   
+      snk_i(i).adr  <= snk_adr_i((i+1)*g_wb_addr_width - 1 downto i*g_wb_addr_width);   
+      snk_i(i).sel  <= snk_sel_i((i+1)*g_wb_sel_width  - 1 downto i*g_wb_sel_width);   
      snk_i(i).cyc  <= snk_cyc_i(i);   
      snk_i(i).stb  <= snk_stb_i(i);   
      snk_i(i).we   <= snk_we_i(i);    
@@ -172,9 +188,9 @@ architecture rtl of swc_core is
      snk_err_o(i)  <= snk_o(i).err;
      snk_rty_o(i)  <= snk_o(i).rty;
  
-      src_dat_o((i+1)*16 - 1 downto i*16) <= src_o(i).dat;   
-      src_adr_o((i+1)*2  - 1 downto i*2)  <= src_o(i).adr;
-      src_sel_o((i+1)*2  - 1 downto i*2)  <= src_o(i).sel;   
+      src_dat_o((i+1)*g_wb_data_width - 1 downto i*g_wb_data_width) <= src_o(i).dat;   
+      src_adr_o((i+1)*g_wb_addr_width - 1 downto i*g_wb_addr_width)  <= src_o(i).adr;
+      src_sel_o((i+1)*g_wb_sel_width  - 1 downto i*g_wb_sel_width )  <= src_o(i).sel;   
      src_cyc_o(i)                        <= src_o(i).cyc;   
      src_stb_o(i)                        <= src_o(i).stb;   
      src_we_o(i)                         <= src_o(i).we;    

--- a/modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd
+++ b/modules/wrsw_swcore/swc_pck_transfer_arbiter.vhd
@@ -103,13 +103,13 @@ architecture syn of swc_pck_transfer_arbiter is


  subtype t_pageaddr is std_logic_vector(g_page_addr_width - 1 downto 0);
-  subtype t_prio is std_logic_vector(g_prio_width - 1 downto 0);
-  subtype t_mask is std_logic_vector(g_num_ports - 1 downto 0);
+  subtype t_prio     is std_logic_vector(g_prio_width - 1 downto 0);
+  subtype t_mask     is std_logic_vector(g_num_ports - 1 downto 0);
  subtype t_pck_size is std_logic_vector(g_max_pck_size_width - 1 downto 0);

  type t_pageaddr_array is array (g_num_ports - 1 downto 0) of t_pageaddr;
-  type t_prio_array is array (g_num_ports - 1 downto 0) of t_prio;
-  type t_mask_array is array (g_num_ports - 1 downto 0) of t_mask;
+  type t_prio_array     is array (g_num_ports - 1 downto 0) of t_prio;
+  type t_mask_array     is array (g_num_ports - 1 downto 0) of t_mask;
  type t_pck_size_array is array (g_num_ports - 1 downto 0) of t_pck_size;

 ---------------------------------------------------------------------------
@@ -178,9 +178,9 @@ begin  --arch
    
    for i in 0 to g_num_ports - 1 loop
      pti_transfer_data_valid(i) <= pto_output_mask(f_modulo_numports(sync_cntr + i))(i);
-      pti_pageaddr (i)           <= pto_pageaddr (f_modulo_numports(sync_cntr + i));
-      pti_prio (i)               <= pto_prio (f_modulo_numports(sync_cntr + i));
-      pti_pck_size (i)           <= pto_pck_size (f_modulo_numports(sync_cntr + i));
+      pti_pageaddr (i)           <= pto_pageaddr   (f_modulo_numports(sync_cntr + i));
+      pti_prio (i)               <= pto_prio       (f_modulo_numports(sync_cntr + i));
+      pti_pck_size (i)           <= pto_pck_size   (f_modulo_numports(sync_cntr + i));
    end loop;
    
  end process;
@@ -240,9 +240,9 @@ begin  --arch
        pto_prio_o         => pto_prio (i),
        pto_pck_size_o     => pto_pck_size (i),
        ib_transfer_pck_i  => ib_transfer_pck_i (i),
-        ib_pageaddr_i      => ib_pageaddr_i ((i + 1)*g_page_addr_width - 1 downto i*g_page_addr_width),
-        ib_mask_i          => ib_mask_i ((i + 1)*g_num_ports - 1 downto i*g_num_ports),
-        ib_prio_i          => ib_prio_i ((i + 1)*g_prio_width - 1 downto i*g_prio_width),
+        ib_pageaddr_i      => ib_pageaddr_i ((i + 1)*g_page_addr_width    - 1 downto i*g_page_addr_width),
+        ib_mask_i          => ib_mask_i     ((i + 1)*g_num_ports          - 1 downto i*g_num_ports),
+        ib_prio_i          => ib_prio_i     ((i + 1)*g_prio_width         - 1 downto i*g_prio_width),
        ib_pck_size_i      => ib_pck_size_i ((i + 1)*g_max_pck_size_width - 1 downto i*g_max_pck_size_width),
        ib_transfer_ack_o  => ib_transfer_ack_o (i),
        ib_busy_o          => ib_busy_o (i)
@@ -261,8 +261,8 @@ begin  --arch
        clk_i                     => clk_i,
        rst_n_i                   => rst_n_i,
        ob_transfer_data_valid_o  => ob_data_valid_o (i),
-        ob_pageaddr_o             => ob_pageaddr_o ((i + 1)*g_page_addr_width - 1 downto i*g_page_addr_width),
-        ob_prio_o                 => ob_prio_o ((i + 1)*g_prio_width - 1 downto i*g_prio_width),
+        ob_pageaddr_o             => ob_pageaddr_o ((i + 1)*g_page_addr_width    - 1 downto i*g_page_addr_width),
+        ob_prio_o                 => ob_prio_o     ((i + 1)*g_prio_width         - 1 downto i*g_prio_width),
        ob_pck_size_o             => ob_pck_size_o ((i + 1)*g_max_pck_size_width - 1 downto i*g_max_pck_size_width),
        ob_transfer_data_ack_i    => ob_ack_i (i),
        pti_transfer_data_valid_i => pti_transfer_data_valid(i),

--- a/modules/wrsw_swcore/swc_swcore_pkg.vhd
+++ b/modules/wrsw_swcore/swc_swcore_pkg.vhd
@@ -218,7 +218,7 @@ package swc_swcore_pkg is
  
  end component;
  
-  component xswc_input_block is
+  component xswc_input_block_old is
    generic ( 
      g_page_addr_width                  : integer ;--:= c_swc_page_addr_width;
      g_num_ports                        : integer ;--:= c_swc_num_ports
@@ -289,6 +289,72 @@ package swc_swcore_pkg is
      );
  end component;

+  component xswc_input_block is
+  generic ( 
+    g_page_addr_width                  : integer ;--:= c_swc_page_addr_width;
+    g_num_ports                        : integer ;--:= c_swc_num_ports
+    g_prio_width                       : integer ;--:= c_swc_prio_width;
+    g_max_pck_size_width               : integer ;--:= c_swc_max_pck_size_width  
+    g_usecount_width                   : integer ;--:= c_swc_usecount_width
+    g_input_block_cannot_accept_data   : string  ;--:= "drop_pck"; --"stall_o", "rty_o" -- Don't CHANGE !
+
+    -- new
+    g_mpm_data_width                   : integer ; -- it needs to be wb_data_width + wb_addr_width
+    g_page_size                        : integer ;
+    g_partial_select_width             : integer ;
+
+    -- probably useless with new memory
+    g_ctrl_width                       : integer ;--:= c_swc_ctrl_width
+    g_packet_mem_multiply              : integer ;--:= c_swc_packet_mem_multiply
+    g_input_block_fifo_size            : integer ;--:= c_swc_input_fifo_size
+    g_input_block_fifo_full_in_advance : integer  --:=c_swc_fifo_full_in_advance
+  );
+  port (
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+    snk_i : in  t_wrf_sink_in;
+    snk_o : out t_wrf_sink_out;
+
+    mmu_page_alloc_req_o : out std_logic;
+    mmu_page_alloc_done_i : in std_logic;
+    mmu_pageaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
+    mmu_pageaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
+    mmu_force_free_o     : out std_logic;
+    mmu_force_free_done_i : in std_logic;
+    mmu_force_free_addr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
+    mmu_set_usecnt_o     : out std_logic;
+    mmu_set_usecnt_done_i : in std_logic;
+    mmu_usecnt_o        : out std_logic_vector(g_usecount_width - 1 downto 0);
+    mmu_nomem_i         : in std_logic;
+
+    rtu_rsp_valid_i     : in  std_logic;
+    rtu_rsp_ack_o       : out std_logic;
+    rtu_dst_port_mask_i : in  std_logic_vector(g_num_ports - 1 downto 0);
+    rtu_drop_i          : in  std_logic;
+    rtu_prio_i          : in  std_logic_vector(g_prio_width - 1 downto 0);
+
+    mpm_data_o           : out std_logic_vector(g_mpm_data_width - 1 downto 0);
+    mpm_dvalid_o         : out std_logic;
+    mpm_dlast_o          : out std_logic;
+    mpm_pg_addr_o        : out std_logic_vector(g_page_addr_width - 1 downto 0);
+    mpm_pg_req_i         : in std_logic;
+    mpm_dreq_i           : in std_logic;
+
+    ll_addr_o : out std_logic_vector(g_page_addr_width -1 downto 0);
+    ll_data_o    : out std_logic_vector(g_page_addr_width + 1 downto 0);
+    ll_wr_req_o   : out std_logic;
+    ll_wr_done_i  : in std_logic;
+
+    pta_transfer_pck_o : out std_logic;
+    pta_transfer_ack_i : in std_logic;
+    pta_pageaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
+    pta_mask_o : out std_logic_vector(g_num_ports - 1 downto 0);
+    pta_pck_size_o : out std_logic_vector(g_max_pck_size_width - 1 downto 0);
+    pta_prio_o : out std_logic_vector(g_prio_width - 1 downto 0)
+
+    );
+  end component;

  component swc_multiport_page_allocator is
    generic ( 
@@ -570,33 +636,41 @@ component  swc_multiport_pck_pg_free_module is
  
  component xswc_core is
    generic( 
-      g_mem_size                         : integer ;--:= c_swc_packet_mem_size
-      g_page_size                        : integer ;--:= c_swc_page_size
      g_prio_num                         : integer ;--:= c_swc_output_prio_num;
      g_max_pck_size                     : integer ;--:= c_swc_max_pck_size
      g_num_ports                        : integer ;--:= c_swc_num_ports
-      g_data_width                       : integer ;--:= c_swc_data_width
-      g_ctrl_width                       : integer ; --:= c_swc_ctrl_width
      g_pck_pg_free_fifo_size            : integer ; --:= c_swc_freeing_fifo_size (in pck_pg_free_module.vhd)
      g_input_block_cannot_accept_data   : string  ;--:= "drop_pck"; --"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
      g_output_block_per_prio_fifo_size  : integer ; --:= c_swc_output_fifo_size    (xswc_output_block)
+
+      -- new
+      g_wb_data_width                    : integer ;
+      g_wb_addr_width                    : integer ;
+      g_wb_sel_width                     : integer ;
+      g_mpm_mem_size                     : integer ;
+      g_mpm_page_size                    : integer ;
+      g_mpm_ratio                        : integer ;
+      g_mpm_fifo_size                    : integer ;
+    
      -- probably useless with new memory
+      g_ctrl_width                       : integer ; --:= c_swc_ctrl_width
      g_packet_mem_multiply              : integer ;--:= c_swc_packet_mem_multiply (xswc_input_block, )
      g_input_block_fifo_size            : integer ;--:= c_swc_input_fifo_size     (xswc_input_block)
-      g_input_block_fifo_full_in_advance : integer --:=c_swc_fifo_full_in_advance (xswc_input_block)
+      g_input_block_fifo_full_in_advance : integer  --:=c_swc_fifo_full_in_advance (xswc_input_block)
      );
-      port (
-      clk_i   : in std_logic;
-      rst_n_i : in std_logic;
+   port (
+      clk_i          : in std_logic;
+      clk_mpm_core_i : in std_logic;
+      rst_n_i        : in std_logic;
  
-      snk_i : in  t_wrf_sink_in_array(g_num_ports-1 downto 0);
-      snk_o : out t_wrf_sink_out_array(g_num_ports-1 downto 0);
+      snk_i          : in  t_wrf_sink_in_array(g_num_ports-1 downto 0);
+      snk_o          : out t_wrf_sink_out_array(g_num_ports-1 downto 0);
  
-      src_i : in  t_wrf_source_in_array(g_num_ports-1 downto 0);
-      src_o : out t_wrf_source_out_array(g_num_ports-1 downto 0);
+      src_i          : in  t_wrf_source_in_array(g_num_ports-1 downto 0);
+      src_o          : out t_wrf_source_out_array(g_num_ports-1 downto 0);
      
-      rtu_rsp_i           : in t_rtu_response_array(g_num_ports  - 1 downto 0);
-      rtu_ack_o          : out std_logic_vector(g_num_ports  - 1 downto 0)
+      rtu_rsp_i      : in t_rtu_response_array(g_num_ports  - 1 downto 0);
+      rtu_ack_o      : out std_logic_vector(g_num_ports  - 1 downto 0)
      );
  end component;


--- a/modules/wrsw_swcore/xswc_core.vhd
+++ b/modules/wrsw_swcore/xswc_core.vhd
--- a/modules/wrsw_swcore/xswc_input_block.vhd
+++ b/modules/wrsw_swcore/xswc_input_block.vhd
--- a/testbench/swcore/swc_core_7ports.sv
+++ b/testbench/swcore/swc_core_7ports.sv
 // Fabric emulator example, showing 2 fabric emulators connected together and exchanging packets.

-`define c_clock_period        8
+`define c_clock_period        16
+`define c_core_clock_period   (`c_clock_period/5)
 `define c_wrsw_prio_width     3
 `define c_swc_ctrl_width      4
 `define c_swc_data_width      16
@@ -43,10 +44,12 @@ module main_7ports;


   
-   reg clk  = 1'b0;
-   reg rst_n = 1'b0;
+   reg clk           = 1'b0;
+   reg clk_mpm_core  = 1'b0;
+   reg rst_n         = 1'b0;
   // generate clock and reset signals
-   always #(`c_clock_period/2) clk <= ~clk;
+   always #(`c_clock_period/2)     clk <= ~clk;
+   always #(`c_core_clock_period/2) clk_mpm_core <= ~clk_mpm_core;
   initial begin 
      repeat(3) @(posedge clk);
      rst_n <= 1'b1;
@@ -96,6 +99,7 @@ module main_7ports;
   xswc_core_wrapper_7ports
    DUT_xswc_core_wrapper(
    .clk_i                 (clk),
+    .clk_mpm_core_i        (clk_mpm_core),
    .rst_n_i               (rst_n),
 //-------------------------------------------------------------------------------
 //-- pWB slave - this is output of the swcore (internally connected to the source)

--- a/testbench/swcore/swc_core_generic.sv
+++ b/testbench/swcore/swc_core_generic.sv
@@ -42,7 +42,8 @@
 -- 2012-02-07  1.0      mlipinsk Created
 ------------------------------------------------------------------------------*/

-`define c_clock_period        8
+`define c_clock_period        16
+`define c_core_clock_period   (`c_clock_period/5)
 `define c_n_pcks_to_send      10
 `timescale 1ns / 1ps

@@ -77,10 +78,12 @@ EthPacket swc_matrix[`c_num_ports][`c_n_pcks_to_send];

 module main_generic;
  
-   reg clk  = 1'b0;
-   reg rst_n = 1'b0;
+   reg clk          = 1'b0;
+   reg clk_mpm_core = 1'b0;
+   reg rst_n        = 1'b0;
   // generate clock and reset signals
-   always #(`c_clock_period/2) clk <= ~clk;
+   always #(`c_clock_period/2)     clk <= ~clk;
+   always #(`c_core_clock_period/2) clk_mpm_core <= ~clk_mpm_core;
   initial begin 
      repeat(3) @(posedge clk);
      rst_n <= 1'b1;
@@ -117,6 +120,7 @@ module main_generic;
   swc_core_wrapper_generic
    DUT_xswcore_wrapper (
    .clk_i                 (clk),
+    .clk_mpm_core_i        (clk_mpm_core),
    .rst_n_i               (rst_n),
    .snk (U_wrf_sink),
    .src(U_wrf_source),
@@ -381,7 +385,7 @@ module main_generic;
      EthPacket      pkt, tmpl;
      EthPacket      txed[$];
      EthPacketGenerator gen;
-      int i;
+      int i,j;
      int n_ports = `c_num_ports;
      bit [`c_num_ports:0] mask;
      // initialization
@@ -394,12 +398,23 @@ module main_generic;
      @(posedge clk);
      wait_cycles(500);
      
-      send_random_packet(src,txed, 0 /*port*/, 0 /*drop*/,7 /*prio*/, 2 /*mask*/);    
-  
-       for(i=0; i<(2*`c_num_ports - 1); i++) begin  
-	 mask = mask^(1<<(i%(`c_num_ports)));
-         send_random_packet(src,txed, i%(`c_num_ports), 0,7 , mask);  
-         wait_cycles(500);
+      for(j=0;j<100;j++)
+        send_random_packet(src,txed, 0 /*port*/, 0 /*drop*/,7 /*prio*/, 2 /*mask*/);    
+
+      //for(j=0;j<`c_num_ports;j++) begin
+      for(j=0;j<16;j++) begin
+	fork 
+	  automatic int  p = j;
+          for(i=0; i<20; i++) begin  
+	    //mask = mask^(1<<(i%(`c_num_ports)));
+	    mask =1<<p;
+            //send_random_packet(src,txed, 0 , 0,7 , mask);  
+            //send_random_packet(src,txed, j, 0,7 , 16'hFFFF);
+            //$display("in fork %d",p);
+	    send_random_packet(src,txed, p, 0,7 , mask);  
+          end
+        join
+         //wait_cycles(500);
       end 
  
  wait_cycles(80000); 

--- a/testbench/swcore/swc_core_wrapper_7ports.vhd
+++ b/testbench/swcore/swc_core_wrapper_7ports.vhd
@@ -59,8 +59,9 @@ entity swc_core_wrapper_7ports is
 	  
        );
  port (
-    clk_i   : in std_logic;
-    rst_n_i : in std_logic;
+    clk_i          : in std_logic;
+    clk_mpm_core_i : in std_logic;
+    rst_n_i        : in std_logic;

 -------------------------------------------------------------------------------
 -- Fabric I/F : input (comes from the Endpoint)
@@ -250,22 +251,30 @@ begin

 U_xswc_core: xswc_core
  generic map(
-    g_mem_size                         => 65536,
-    g_page_size                        => 64,
    g_prio_num                         => 8,
    g_max_pck_size                     => 10 * 1024,
    g_num_ports                        => 7,
-    g_data_width                       => 16,
-    g_ctrl_width                       => 4,
    g_pck_pg_free_fifo_size            => ((65536/64)/2) ,
    g_input_block_cannot_accept_data   => "drop_pck",
    g_output_block_per_prio_fifo_size  => 64,
+    
+    g_wb_data_width                    => 16,
+    g_wb_addr_width                    => 2,
+    g_wb_sel_width                     => 2,
+    
+    g_mpm_mem_size                     => 65536,
+    g_mpm_page_size                    => 64,
+    g_mpm_ratio                        => 2,
+    g_mpm_fifo_size                    => 4,
+
+    g_ctrl_width                       => 4,
    g_packet_mem_multiply              => 16,
    g_input_block_fifo_size            => (2 * 16),
    g_input_block_fifo_full_in_advance => ((2 * 16) - 3)
  )
  port map(
    clk_i               => clk_i,
+    clk_mpm_core_i      => clk_mpm_core_i,
    rst_n_i             => rst_n_i,

    snk_i               => snk_i,

--- a/testbench/swcore/swc_core_wrapper_generic.svh
+++ b/testbench/swcore/swc_core_wrapper_generic.svh
@@ -8,6 +8,7 @@
 module swc_core_wrapper_generic
  (
   clk_i,
+   clk_mpm_core_i,
   rst_n_i,
   src,
   snk,
@@ -21,6 +22,7 @@ module swc_core_wrapper_generic
   );

   input clk_i;
+   input clk_mpm_core_i;
   input rst_n_i;

   IWishboneMaster  #(2,16) src[`c_num_ports] (clk_i,rst_n_i);
@@ -55,22 +57,30 @@ module swc_core_wrapper_generic
   
   swc_core
     #(
-       .g_mem_size                         (`c_mem_size),
-       .g_page_size                        (`c_page_size),
       .g_prio_num                         (`c_prio_num),
       .g_max_pck_size                     (`c_max_pck_size),
       .g_num_ports                        (`c_num_ports),
-       .g_data_width                       (`c_data_width),
-       .g_ctrl_width                       (`c_ctrl_width),
       .g_pck_pg_free_fifo_size            (`c_pck_pg_free_fifo_size),
       .g_input_block_cannot_accept_data   (`c_input_block_cannot_accept_data),
       .g_output_block_per_prio_fifo_size  (`c_output_block_per_prio_fifo_size),
+
+       .g_wb_data_width                    (`c_wb_data_width),
+       .g_wb_addr_width                    (`c_wb_addr_width),
+       .g_wb_sel_width                     (`c_wb_sel_width),
+
+       .g_mpm_mem_size                     (`c_mpm_mem_size),
+       .g_mpm_page_size                    (`c_mpm_page_size),
+       .g_mpm_ratio                        (`c_mpm_ratio),
+       .g_mpm_fifo_size                    (`c_mpm_fifo_size),
+
+       .g_ctrl_width                       (`c_ctrl_width),
       .g_packet_mem_multiply              (`c_packet_mem_multiply),
       .g_input_block_fifo_size            (`c_input_block_fifo_size),
       .g_input_block_fifo_full_in_advance (`c_input_block_fifo_full_in_advance)
       ) DUT_swc_core(
-              .clk_i (clk_i),
-              .rst_n_i (rst_n_i),
+              .clk_i               (clk_i),
+              .clk_mpm_core_i      (clk_mpm_core_i),
+              .rst_n_i             (rst_n_i),

              .snk_dat_i           (snk_dat),
              .snk_adr_i           (snk_adr),

--- a/testbench/swcore/swc_param_defs.svh
+++ b/testbench/swcore/swc_param_defs.svh
@@ -24,18 +24,25 @@
 `define  c_num_ports                         16 //MAX: 16     //
 ////////////////////////////////////////////////////////////////

-
-
-`define  c_mem_size                          65536            //c_swc_packet_mem_size,
-`define  c_page_size                         64               //c_swc_page_size,
 `define  c_prio_num                          8                // c_swc_output_prio_num,
 `define  c_max_pck_size                      10 * 1024        // 10kB -- c_swc_max_pck_size,
-`define  c_data_width                        16               //c_swc_data_width,
-`define  c_ctrl_width                        4                //c_swc_ctrl_width,
+
+`define  c_mpm_mem_size                      65536            //c_swc_packet_mem_size,
+`define  c_mpm_page_size                     64               //c_swc_page_size,
+`define  c_mpm_ratio                         2
+`define  c_mpm_fifo_size                     4
+
+// these are hard-coded into testbench
+`define  c_wb_data_width                     16               //c_swc_data_width,
+`define  c_wb_addr_width                     2                //
+`define  c_wb_sel_width                      2                //
+
 `define  c_pck_pg_free_fifo_size            ((65536/64)/2)    //c_swc_freeing_fifo_size,
 `define  c_input_block_cannot_accept_data    "drop_pck"       //"stall_o", "rty_o" -- (xswc_input_block) Don't CHANGE !
 `define  c_output_block_per_prio_fifo_size   64               //c_swc_output_fifo_size,

+
+`define  c_ctrl_width                        4                //c_swc_ctrl_width,
 `define  c_packet_mem_multiply               16               //c_swc_packet_mem_multiply,
 `define  c_input_block_fifo_size             (2 * 16)         //c_swc_input_fifo_size,     
 `define  c_input_block_fifo_full_in_advance ((2 * 16) - 3)    // c_swc_fifo_full_in_advance

--- a/testbench/swcore/xswc_core_wrapper_7ports.svh
+++ b/testbench/swcore/xswc_core_wrapper_7ports.svh
@@ -31,6 +31,7 @@
 module xswc_core_wrapper_7ports
  (
   input clk_i,
+   input clk_mpm_core_i,
   input rst_n_i,

   // input to the wrapper, this is connected to the sink of the xswc_core
@@ -67,6 +68,7 @@ module xswc_core_wrapper_7ports
       .g_swc_prio_width(`PORT_PRIO_W)
       ) DUT_swc_core_7ports_wrapper (
              .clk_i (clk_i),
+              .clk_mpm_core_i(clk_mpm_core_i),
              .rst_n_i (rst_n_i),