[SWcore] bugfix in the input_block of swcore-> handling exception of not…

[SWcore] bugfix in the input_block of swcore-> handling exception of not receiving RTU decision when packet is corrupted

[SWcore] bugfix in the input_block of swcore-> handling exception of not…
[SWcore] bugfix in the input_block of swcore-> handling exception of not receiving RTU decision when packet is corrupted
7d3ded2a · Maciej Lipinski · 0d580948 · 7d3ded2a · 7d3ded2a · 7d3ded2a
Commit 7d3ded2a authored May 10, 2013 by Maciej Lipinski
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Showing with 44 additions and 4 deletions

xswc_input_block.vhd modules/wrsw_swcore/xswc_input_block.vhd +6 -1

main.sv testbench/scb_top/main.sv +37 -2

scb_top_bare.vhd top/bare_top/scb_top_bare.vhd +1 -1

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--- a/modules/wrsw_swcore/xswc_input_block.vhd
+++ b/modules/wrsw_swcore/xswc_input_block.vhd
@@ -1530,8 +1530,12 @@ begin
        when S_WAIT_RTU_VALID =>
          --===========================================================================================
+          -- error coming from rcv_pck FSM, ignore transfer
+          if (rp_in_pck_error = '1') then
+              s_transfer_pck <= S_DROP;
          -- RTU decision received
-          if(rtu_rsp_ack = '1') then
+          elsif(rtu_rsp_ack = '1') then
            -- error coming from rcv_pck FSM or RTU decisio no drop, both cases, ignore transfer
            if (rp_in_pck_error = '1' or tp_drop = '1') then
@@ -1564,6 +1568,7 @@ begin
          --===========================================================================================
        when S_WAIT_SOF =>
          --===========================================================================================
          if(in_pck_sof = '1') then
            -- don't need to set usecnt

--- a/testbench/scb_top/main.sv
+++ b/testbench/scb_top/main.sv
@@ -1326,7 +1326,7 @@ module main;
   * stress test: 18 ports with packets, no gap - page-allocation too slow...
   * 
   **/
-//*
+/*
  initial begin
    portUnderTest        = 18'b111111111111111111;
    repeat_number        = 30;
@@ -1334,7 +1334,7 @@ module main;
    g_enable_pck_gaps    = 0;
    g_force_payload_size = 512;
  end
-//*/
+*/
   /** ***************************   test scenario 45  ************************************* **/
  /*
   * test HP detection by prio - works
@@ -1396,6 +1396,29 @@ module main;
    g_force_payload_size = 512;
  end
 */
+   /** ***************************   test scenario 42  ************************************* **/ 
+  /*
+   * testing switch over between ports 1,2
+   * trying to simulate situation which happens in hw: stuck at S_WAIT_RTU_VALID,
+   * 
+   **/
+//*
+  initial begin
+    portUnderTest        = 18'b000000000000000110;
+    g_tru_enable         = 1;
+    g_failure_scenario   = 11;
+                         // tx  ,rx ,opt
+    trans_paths[1]       = '{1  ,6 , 7 };
+    trans_paths[2]       = '{2  ,7 , 7 };
+    repeat_number        = 30;
+    g_active_port        = 1;
+    g_backup_port        = 2;    
+    tries_number         = 1;
+    tru_config_opt       = 3;
+    g_enable_pck_gaps    = 0;
+    g_force_payload_size = 512;
+  end
+//*/
 //////////////////////////////////////////////////////////////////////////////////////////////
 //////////////////////////////////////////////////////////////////////////////////////////////
 //////////////////////////////////////////////////////////////////////////////////////////////
@@ -2412,6 +2435,18 @@ module main;
             hwdu.dump_mpm_page_utilization(1);
           end        
+           if(g_failure_scenario == 11)
+           begin 
+             int thrash_cnt = 1;
+             wait_cycles(2015);
+             ep_ctrl[g_active_port] = 'b0;
+             $display("");
+             $display(">>>>>>>>>>>>>>>>>>>>>>>>>>>>> link 0 down <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
+             $display("");
+             wait_cycles(100);
+             hwdu.dump_mpm_page_utilization(1);
+           end  
         end 
      join_none; //

--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -139,7 +139,7 @@ end scb_top_bare;
 architecture rtl of scb_top_bare is
-  constant c_GW_VERSION    : std_logic_vector(31 downto 0) := x"09_05_13_02"; --DD_MM_YY_VV
+  constant c_GW_VERSION    : std_logic_vector(31 downto 0) := x"10_05_13_00"; --DD_MM_YY_VV
  constant c_NUM_WB_SLAVES : integer := 16;
  constant c_NUM_PORTS     : integer := g_num_ports;
  constant c_MAX_PORTS     : integer := 18;