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White Rabbit Switch - Gateware
Commit 7ec1f1a1 authored by José López Jiménez's avatar José López Jiménez
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Support for UART in holdover exp board 

Also, doubled size of U_DPRAM
parent cd61fa8a
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Showing with 52 additions and 35 deletions
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 7ec1f1a1
...@@ -82,6 +82,9 @@ entity wrsw_rt_subsystem is ...@@ -82,6 +82,9 @@ entity wrsw_rt_subsystem is
ho_dac_sclk_o : out std_logic; ho_dac_sclk_o : out std_logic;
ho_dac_data_o : out std_logic; ho_dac_data_o : out std_logic;
ho_uart_tx_o : out std_logic;
ho_uart_rx_i : in std_logic;
-- Debug UART -- Debug UART
uart_txd_o : out std_logic; uart_txd_o : out std_logic;
uart_rxd_i : in std_logic; uart_rxd_i : in std_logic;
...@@ -235,7 +238,7 @@ architecture rtl of wrsw_rt_subsystem is ...@@ -235,7 +238,7 @@ architecture rtl of wrsw_rt_subsystem is
-- 0x10400 - 0x10500: Timer -- 0x10400 - 0x10500: Timer
constant c_NUM_GPIO_PINS : integer := 9; constant c_NUM_GPIO_PINS : integer := 9;
constant c_NUM_WB_SLAVES : integer := 9; constant c_NUM_WB_SLAVES : integer := 10;
constant c_MASTER_CPU : integer := 0; constant c_MASTER_CPU : integer := 0;
constant c_MASTER_LM32 : integer := 1; constant c_MASTER_LM32 : integer := 1;
...@@ -248,7 +251,8 @@ architecture rtl of wrsw_rt_subsystem is ...@@ -248,7 +251,8 @@ architecture rtl of wrsw_rt_subsystem is
constant c_SLAVE_TIMER : integer := 5; constant c_SLAVE_TIMER : integer := 5;
constant c_SLAVE_PPSGEN : integer := 6; constant c_SLAVE_PPSGEN : integer := 6;
constant c_SLAVE_GEN10 : integer := 7; constant c_SLAVE_GEN10 : integer := 7;
constant c_SLAVE_SPI_GM : integer := 8; constant c_SLAVE_SPI_GM : integer := 8;
constant c_SLAVE_HO_UART : integer := 9;
signal cnx_slave_in : t_wishbone_slave_in_array(1 downto 0); signal cnx_slave_in : t_wishbone_slave_in_array(1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(1 downto 0); signal cnx_slave_out : t_wishbone_slave_out_array(1 downto 0);
...@@ -324,7 +328,7 @@ begin -- rtl ...@@ -324,7 +328,7 @@ begin -- rtl
U_DPRAM : xwb_dpram U_DPRAM : xwb_dpram
generic map ( generic map (
g_size => 16384, g_size => 32768,
g_init_file => "", g_init_file => "",
g_slave1_interface_mode => PIPELINED, g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED, g_slave2_interface_mode => PIPELINED,
...@@ -338,7 +342,7 @@ begin -- rtl ...@@ -338,7 +342,7 @@ begin -- rtl
slave2_i => cpu_iwb_out, slave2_i => cpu_iwb_out,
slave2_o => cpu_iwb_in); slave2_o => cpu_iwb_in);
U_UART : xwb_simple_uart U_LM32_UART : xwb_simple_uart
generic map ( generic map (
g_with_virtual_uart => true, g_with_virtual_uart => true,
g_with_physical_uart => true, g_with_physical_uart => true,
...@@ -353,6 +357,21 @@ begin -- rtl ...@@ -353,6 +357,21 @@ begin -- rtl
uart_rxd_i => uart_rxd_i, uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o); uart_txd_o => uart_txd_o);
U_HO_UART : xwb_simple_uart
generic map (
g_with_virtual_uart => false,
g_with_physical_uart => true,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => cnx_master_out(c_SLAVE_HO_UART),
slave_o => cnx_master_in(c_SLAVE_HO_UART),
desc_o => open,
uart_rxd_i => ho_uart_rx_i,
uart_txd_o => ho_uart_tx_o);
U_SoftPLL : xwr_softpll_ng U_SoftPLL : xwr_softpll_ng
generic map ( generic map (
......
top/bare_top/scb_top_bare.vhd
View file @ 7ec1f1a1
...@@ -122,6 +122,9 @@ entity scb_top_bare is ...@@ -122,6 +122,9 @@ entity scb_top_bare is
ho_dac_sync_n_o : out std_logic; ho_dac_sync_n_o : out std_logic;
ho_dac_sclk_o : out std_logic; ho_dac_sclk_o : out std_logic;
ho_dac_data_o : out std_logic; ho_dac_data_o : out std_logic;
ho_uart_tx_o : out std_logic;
ho_uart_rx_i : in std_logic;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- AD9516 PLL Control signals -- AD9516 PLL Control signals
...@@ -548,6 +551,8 @@ begin ...@@ -548,6 +551,8 @@ begin
ho_dac_sync_n_o => ho_dac_sync_n_o, ho_dac_sync_n_o => ho_dac_sync_n_o,
ho_dac_sclk_o => ho_dac_sclk_o, ho_dac_sclk_o => ho_dac_sclk_o,
ho_dac_data_o => ho_dac_data_o, ho_dac_data_o => ho_dac_data_o,
ho_uart_tx_o => ho_uart_tx_o,
ho_uart_rx_i => ho_uart_rx_i,
uart_txd_o => uart_txd_o, uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i, uart_rxd_i => uart_rxd_i,
......
top/bare_top/wrs_sdb_pkg.vhd
View file @ 7ec1f1a1
...@@ -237,7 +237,7 @@ package wrs_sdb_pkg is ...@@ -237,7 +237,7 @@ package wrs_sdb_pkg is
name => "WRSW SWCORE "))); name => "WRSW SWCORE ")));
-- RT subsystem crossbar -- RT subsystem crossbar
constant c_rtbar_layout : t_sdb_record_array(8 downto 0) := constant c_rtbar_layout : t_sdb_record_array(9 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(16384), x"00000000"), (0 => f_sdb_embed_device(f_xwb_dpram(16384), x"00000000"),
1 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00010000"), --UART 1 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00010000"), --UART
2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00010100"), --SoftPLL 2 => f_sdb_embed_device(c_xwr_softpll_ng_sdb, x"00010100"), --SoftPLL
...@@ -246,9 +246,10 @@ package wrs_sdb_pkg is ...@@ -246,9 +246,10 @@ package wrs_sdb_pkg is
5 => f_sdb_embed_device(c_xwb_tics_sdb, x"00010400"), --TICS 5 => f_sdb_embed_device(c_xwb_tics_sdb, x"00010400"), --TICS
6 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00010500"), --PPSgen 6 => f_sdb_embed_device(c_xwr_pps_gen_sdb, x"00010500"), --PPSgen
7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"), --GEN 10MHz 7 => f_sdb_embed_device(c_xwrsw_gen_10mhz, x"00010600"), --GEN 10MHz
8 => f_sdb_embed_device(c_xwb_spi_sdb, x"00010700")); --SPI ext 8 => f_sdb_embed_device(c_xwb_spi_sdb, x"00010700"), --SPI ext
9 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00010800")); --SPI ext
constant c_rtbar_sdb_address : t_wishbone_address := x"00010800"; constant c_rtbar_sdb_address : t_wishbone_address := x"00011000";
constant c_rtbar_bridge_sdb : t_sdb_bridge := constant c_rtbar_bridge_sdb : t_sdb_bridge :=
f_xwb_bridge_layout_sdb(true, c_rtbar_layout, c_rtbar_sdb_address); f_xwb_bridge_layout_sdb(true, c_rtbar_layout, c_rtbar_sdb_address);
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 7ec1f1a1
...@@ -232,6 +232,8 @@ package wrsw_top_pkg is ...@@ -232,6 +232,8 @@ package wrsw_top_pkg is
ho_dac_sync_n_o : out std_logic; ho_dac_sync_n_o : out std_logic;
ho_dac_sclk_o : out std_logic; ho_dac_sclk_o : out std_logic;
ho_dac_data_o : out std_logic; ho_dac_data_o : out std_logic;
ho_uart_tx_o : out std_logic;
ho_uart_rx_i : in std_logic;
uart_txd_o : out std_logic; uart_txd_o : out std_logic;
uart_rxd_i : in std_logic; uart_rxd_i : in std_logic;
pps_csync_o : out std_logic; pps_csync_o : out std_logic;
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ 7ec1f1a1
...@@ -146,8 +146,8 @@ NET "clk_en_o" LOC = AD16; ...@@ -146,8 +146,8 @@ NET "clk_en_o" LOC = AD16;
NET "clk_sel_o" LOC = AK16; # clk1_sel, set to zero in scb_top_bare NET "clk_sel_o" LOC = AK16; # clk1_sel, set to zero in scb_top_bare
# Holdover expansion board # Holdover expansion board
NET "ho_fpga_tx_o" LOC = B22; NET "ho_uart_tx_o" LOC = B22;
NET "ho_fpga_rx_i" LOC = C22; NET "ho_uart_rx_i" LOC = C22;
NET "ho_dac_sclk_o" LOC = A23; NET "ho_dac_sclk_o" LOC = A23;
NET "ho_dac_data_o" LOC = A24; NET "ho_dac_data_o" LOC = A24;
......
top/scb_18ports/scb_top_synthesis.vhd
View file @ 7ec1f1a1
...@@ -142,8 +142,8 @@ entity scb_top_synthesis is ...@@ -142,8 +142,8 @@ entity scb_top_synthesis is
uart_rxd_i : in std_logic; uart_rxd_i : in std_logic;
ho_fpga_tx_o : out std_logic; ho_uart_tx_o : out std_logic;
ho_fpga_rx_i : in std_logic; ho_uart_rx_i : in std_logic;
ho_dac_sclk_o : out std_logic; ho_dac_sclk_o : out std_logic;
ho_dac_data_o : out std_logic; ho_dac_data_o : out std_logic;
...@@ -291,14 +291,6 @@ architecture Behavioral of scb_top_synthesis is ...@@ -291,14 +291,6 @@ architecture Behavioral of scb_top_synthesis is
signal i2c_sda_in : std_logic_vector(3 downto 0); signal i2c_sda_in : std_logic_vector(3 downto 0);
signal i2c_scl_in : std_logic_vector(3 downto 0); signal i2c_scl_in : std_logic_vector(3 downto 0);
-- Moved all this to an additional position in the vector above:
-- signal ho_temp_scl_in : std_logic;
-- signal ho_temp_sda_in : std_logic;
-- signal ho_temp_scl_out : std_logic;
-- signal ho_temp_sda_out : std_logic;
-- signal ho_temp_scl_oen : std_logic;
-- signal ho_temp_sda_oen : std_logic;
attribute buffer_type : string; attribute buffer_type : string;
attribute buffer_type of clk_dmtd : signal is "BUFG"; attribute buffer_type of clk_dmtd : signal is "BUFG";
attribute buffer_type of clk_ref : signal is "BUFG"; attribute buffer_type of clk_ref : signal is "BUFG";
...@@ -353,9 +345,11 @@ architecture Behavioral of scb_top_synthesis is ...@@ -353,9 +345,11 @@ architecture Behavioral of scb_top_synthesis is
dac_main_sync_n_o : out std_logic; dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic; dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic; dac_main_data_o : out std_logic;
ho_dac_sync_n_o : out std_logic; ho_dac_sync_n_o : out std_logic;
ho_dac_sclk_o : out std_logic; ho_dac_sclk_o : out std_logic;
ho_dac_data_o : out std_logic; ho_dac_data_o : out std_logic;
ho_uart_tx_o : out std_logic;
ho_uart_rx_i : in std_logic;
pll_status_i : in std_logic; pll_status_i : in std_logic;
pll_mosi_o : out std_logic; pll_mosi_o : out std_logic;
pll_miso_i : in std_logic; pll_miso_i : in std_logic;
...@@ -363,18 +357,18 @@ architecture Behavioral of scb_top_synthesis is ...@@ -363,18 +357,18 @@ architecture Behavioral of scb_top_synthesis is
pll_cs_n_o : out std_logic; pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic; pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic; pll_reset_n_o : out std_logic;
gm_pll_mosi_o : out std_logic; gm_pll_mosi_o : out std_logic;
gm_pll_miso_i : in std_logic; gm_pll_miso_i : in std_logic;
gm_pll_sck_o : out std_logic; gm_pll_sck_o : out std_logic;
gm_pll_cs_n_o : out std_logic; gm_pll_cs_n_o : out std_logic;
gm_pll_sync_n_o : out std_logic; gm_pll_sync_n_o : out std_logic;
gm_pll_reset_n_o : out std_logic; gm_pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic; uart_txd_o : out std_logic;
uart_rxd_i : in std_logic; uart_rxd_i : in std_logic;
clk_en_o : out std_logic; clk_en_o : out std_logic;
clk_sel_o : out std_logic; clk_sel_o : out std_logic;
uart_sel_o : out std_logic; uart_sel_o : out std_logic;
p_3v3_vco_en_o : out std_logic; p_3v3_vco_en_o : out std_logic;
phys_o : out t_phyif_output_array(g_num_ports-1 downto 0); phys_o : out t_phyif_output_array(g_num_ports-1 downto 0);
phys_i : in t_phyif_input_array(g_num_ports-1 downto 0); phys_i : in t_phyif_input_array(g_num_ports-1 downto 0);
led_link_o : out std_logic_vector(g_num_ports-1 downto 0); led_link_o : out std_logic_vector(g_num_ports-1 downto 0);
...@@ -811,6 +805,8 @@ begin ...@@ -811,6 +805,8 @@ begin
ho_dac_sync_n_o => ho_dac_sync_n_o, ho_dac_sync_n_o => ho_dac_sync_n_o,
ho_dac_sclk_o => ho_dac_sclk_o, ho_dac_sclk_o => ho_dac_sclk_o,
ho_dac_data_o => ho_dac_data_o, ho_dac_data_o => ho_dac_data_o,
ho_uart_tx_o => ho_uart_tx_o,
ho_uart_rx_i => ho_uart_rx_i,
pll_status_i => pll_status_i, pll_status_i => pll_status_i,
pll_mosi_o => pll_mosi_o, pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i, pll_miso_i => pll_miso_i,
...@@ -841,12 +837,6 @@ begin ...@@ -841,12 +837,6 @@ begin
i2c_sda_oen_o => i2c_sda_oen, i2c_sda_oen_o => i2c_sda_oen,
i2c_sda_o => i2c_sda_out, i2c_sda_o => i2c_sda_out,
i2c_sda_i => i2c_sda_in, i2c_sda_i => i2c_sda_in,
-- ho_temp_scl_oen_o => ho_temp_scl_oen,
-- ho_temp_scl_o => ho_temp_scl_out,
-- ho_temp_scl_i => ho_temp_scl_in,
-- ho_temp_sda_oen_o => ho_temp_sda_oen,
-- ho_temp_sda_o => ho_temp_sda_out,
-- ho_temp_sda_i => ho_temp_sda_in,
mb_fan1_pwm_o => mb_fan1_pwm_o, mb_fan1_pwm_o => mb_fan1_pwm_o,
mb_fan2_pwm_o => mb_fan2_pwm_o, mb_fan2_pwm_o => mb_fan2_pwm_o,
spll_dbg_o => open); spll_dbg_o => open);
......
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