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White Rabbit Switch - Gateware
Commit 870484ed authored by Maciej Lipinski's avatar Maciej Lipinski
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update the mechanism of detecting different WRS-FL versions and dac_sel 

- updated the pin names to reflect the true functionality
- connect only the pin that is used, this is a HACK and will need to be
  changed in the future.
parent 94e1abb0
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Showing with 48 additions and 12 deletions
top/bare_top/scb_top_bare.vhd
View file @ 870484ed
......@@ -120,7 +120,6 @@ entity scb_top_bare is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
dac_sel_i : in std_logic_vector(2 downto 0);
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
......@@ -175,6 +174,12 @@ entity scb_top_bare is
-- UART source selection (FPGA/DBGU)
uart_sel_o : out std_logic;
-------------------------------------------------------------------------------
-- DS1374U-18+
-------------------------------------------------------------------------------
wd_int_i : in std_logic := '1';
wd_scl_i : in std_logic := '1';
wd_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- GTX ports
---------------------------------------------------------------------------
......@@ -476,6 +481,8 @@ architecture rtl of scb_top_bare is
signal dac_main_sclk : std_logic;
signal dac_main_data : std_logic;
signal dac_sel : std_logic_vector(2 downto 0);
begin
......@@ -647,7 +654,7 @@ begin
dac_main_sync_n_o => dac_main_sync_n,
dac_main_sclk_o => dac_main_sclk,
dac_main_data_o => dac_main_data,
dac_sel_i => dac_sel_i,
dac_sel_i => dac_sel,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
......@@ -1362,5 +1369,20 @@ begin
end if;
end process;
----------------------------------------------------------------------
-- Use "unused lines to detect version of WRS-FL hardware: HACK
-- For WRS-FL v1.5: wd_int_i = '0'
-- For all others : wd_int_i = '1'
--
-- As such
-- dac_sel = "001": WRS-FL v1.5
-- dac_sel = "000": all the rest
--
-- TODO: pass info about SCB version from SW (read from EEPROM) to HDL
----------------------------------------------------------------------
dac_sel(0) <= '1' when wd_int_i = '0' else '0';
dac_sel(1) <= '0';
dac_sel(2) <= '0';
end rtl;
top/bare_top/scb_top_sim.vhd
View file @ 870484ed
......@@ -203,7 +203,6 @@ begin -- rtl
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
dac_sel_i => "111",
pll_status_i => pll_status_i,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ 870484ed
......@@ -121,9 +121,10 @@ NET "dac_main_sync_n_o" LOC="AM17";
NET "dac_main_sclk_o" LOC="AN17";
NET "dac_main_data_o" LOC="AP17";
NET "dac_sel_i[0]" LOC="T24";
NET "dac_sel_i[1]" LOC="T23";
NET "dac_sel_i[2]" LOC="AC23";
NET "wd_scl_i" LOC="T24";
NET "wd_sda_b" LOC="T23";
NET "wd_int_i" LOC="AC23";
NET "wd_int_i" PULLUP;# just in case it is not connected in future designs
NET "pll_cs_n_o" LOC="AK18"; # PLL_CS
NET "pll_sck_o" LOC="AE16"; # PLL_SCLK
......
top/scb_18ports/scb_top_synthesis.vhd
View file @ 870484ed
......@@ -117,7 +117,13 @@ entity scb_top_synthesis is
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
dac_sel_i : in std_logic_vector(2 downto 0);
-------------------------------------------------------------------------------
-- DS1374U-18+
-------------------------------------------------------------------------------
wd_int_i : in std_logic;
wd_scl_i : in std_logic;
wd_sda_b : inout std_logic;
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
......@@ -374,7 +380,6 @@ architecture Behavioral of scb_top_synthesis is
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
dac_sel_i : in std_logic_vector(2 downto 0);
ljd_dac_main_sync_n_o : out std_logic;
ljd_dac_main_sclk_o : out std_logic;
ljd_dac_main_data_o : out std_logic;
......@@ -403,6 +408,9 @@ architecture Behavioral of scb_top_synthesis is
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
uart_sel_o : out std_logic;
wd_int_i : in std_logic := '1';
wd_scl_i : in std_logic := '1';
wd_sda_b : inout std_logic;
clk_dmtd_divsel_o : out std_logic;
phys_o : out t_phyif_output_array(g_num_ports-1 downto 0);
phys_i : in t_phyif_input_array(g_num_ports-1 downto 0);
......@@ -493,8 +501,6 @@ architecture Behavioral of scb_top_synthesis is
17 => false
);
dac_sel : std_logic_vector(2 downto 0);
begin
--chipscope_icon_1 : chipscope_icon
......@@ -893,7 +899,6 @@ begin
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
dac_sel_i => dac_sel,
-- Low-jitter daughterboard support
ljd_dac_main_sync_n_o => ljd_dac_main_sync_n_o,
ljd_dac_main_sclk_o => ljd_dac_main_sclk_o,
......@@ -924,6 +929,9 @@ begin
clk_en_o => clk_en_o,
clk_sel_o => clk_sel_o,
-- uart_sel_o => uart_sel_o,
wd_int_i => wd_int_i,
wd_scl_i => wd_scl_i,
wd_sda_b => wd_sda_b,
clk_dmtd_divsel_o => clk_dmtd_divsel_o,
gpio_i => x"00000000",
phys_o => to_phys(c_NUM_PORTS-1 downto 0),
......@@ -954,7 +962,6 @@ begin
sensors_scl_b <= i2c_scl_out(2) when i2c_scl_oen(2) = '0' else 'Z';
sensors_sda_b <= i2c_sda_out(2) when i2c_sda_oen(2) = '0' else 'Z';
dac_sel <= not dac_sel_i;
end Behavioral;
top/scb_8ports/scb_top_synthesis.vhd
View file @ 870484ed
......@@ -157,6 +157,13 @@ entity scb_top_synthesis is
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-------------------------------------------------------------------------------
-- DS1374U-18+
-------------------------------------------------------------------------------
wd_int_i : in std_logic := '1';
wd_scl_i : in std_logic := '1';
wd_sda_b : inout std_logic;
-------------------------------------------------------------------------------
-- Clock fanout control
-------------------------------------------------------------------------------
......
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