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White Rabbit Switch - Gateware
Commit 8d17a35c authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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softpll: use generic to define number of ext channels

parent 1a8c42fa
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Showing with 34 additions and 68 deletions
wr-cores @ 8478786f
Subproject commit 9542d87b1381843b71e3aca0835358817c6e92a6 Subproject commit 8478786f1ed97c507e2f5d04219a5ebc9a31e708
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 8d17a35c
...@@ -46,6 +46,7 @@ entity wrsw_rt_subsystem is ...@@ -46,6 +46,7 @@ entity wrsw_rt_subsystem is
generic ( generic (
g_num_rx_clocks : integer; g_num_rx_clocks : integer;
g_num_ext_clks : integer;
g_simulation : boolean); g_simulation : boolean);
port( port(
...@@ -54,7 +55,7 @@ entity wrsw_rt_subsystem is ...@@ -54,7 +55,7 @@ entity wrsw_rt_subsystem is
clk_dmtd_i : in std_logic; clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0); clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_i : in std_logic; clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic; clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_ext_mul_locked_i : in std_logic; clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic; clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic; clk_aux_n_o : out std_logic;
...@@ -68,7 +69,6 @@ entity wrsw_rt_subsystem is ...@@ -68,7 +69,6 @@ entity wrsw_rt_subsystem is
rst_n_o : out std_logic; rst_n_o : out std_logic;
-- WRS Low jitter daughterboard -- WRS Low jitter daughterboard
clk_ext_db_i : in std_logic;
ext_board_detected_i : in std_logic; ext_board_detected_i : in std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0); ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
...@@ -150,9 +150,8 @@ architecture rtl of wrsw_rt_subsystem is ...@@ -150,9 +150,8 @@ architecture rtl of wrsw_rt_subsystem is
g_tag_bits : integer; g_tag_bits : integer;
g_num_ref_inputs : integer; g_num_ref_inputs : integer;
g_num_outputs : integer; g_num_outputs : integer;
g_num_exts : integer;
g_with_debug_fifo : boolean; g_with_debug_fifo : boolean;
g_with_ext_clock_input : boolean;
g_with_ext_daughterboard : boolean;
g_divide_input_by_2 : boolean; g_divide_input_by_2 : boolean;
g_reverse_dmtds : boolean; g_reverse_dmtds : boolean;
g_ref_clock_rate : integer; g_ref_clock_rate : integer;
...@@ -169,9 +168,8 @@ architecture rtl of wrsw_rt_subsystem is ...@@ -169,9 +168,8 @@ architecture rtl of wrsw_rt_subsystem is
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0); clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic; clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic; clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic; clk_ext_mul_i : in std_logic_vector(g_num_exts-1 downto 0);
clk_ext_mul_locked_i : in std_logic; clk_ext_mul_locked_i : in std_logic;
clk_ext_db_i : in std_logic;
pps_csync_p1_i : in std_logic; pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic; pps_ext_a_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0); dac_dmtd_data_o : out std_logic_vector(15 downto 0);
...@@ -341,9 +339,8 @@ begin -- rtl ...@@ -341,9 +339,8 @@ begin -- rtl
g_address_granularity => BYTE, g_address_granularity => BYTE,
g_num_ref_inputs => g_num_rx_clocks, g_num_ref_inputs => g_num_rx_clocks,
g_num_outputs => 1, g_num_outputs => 1,
g_num_exts => g_num_ext_clks,
g_reverse_dmtds => true, g_reverse_dmtds => true,
g_with_ext_clock_input => true,
g_with_ext_daughterboard => true,
g_divide_input_by_2 => false, g_divide_input_by_2 => false,
g_with_debug_fifo => true, g_with_debug_fifo => true,
g_ref_clock_rate => 62500000, g_ref_clock_rate => 62500000,
...@@ -360,7 +357,6 @@ begin -- rtl ...@@ -360,7 +357,6 @@ begin -- rtl
clk_ext_i => clk_ext_i, clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i, clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i, clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_ext_db_i => clk_ext_db_i,
pps_csync_p1_i => pps_csync, pps_csync_p1_i => pps_csync,
pps_ext_a_i => pps_ext_i, pps_ext_a_i => pps_ext_i,
dac_dmtd_data_o => dac_dmtd_data, dac_dmtd_data_o => dac_dmtd_data,
......
top/bare_top/scb_top_bare.vhd
View file @ 8d17a35c
...@@ -82,7 +82,7 @@ entity scb_top_bare is ...@@ -82,7 +82,7 @@ entity scb_top_bare is
-- for re-phasing the 10 MHz input as well as clocking the -- for re-phasing the 10 MHz input as well as clocking the
clk_aux_i : in std_logic; clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic; clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i : in std_logic; clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic; -- going to CLK2 SMC on the front pannel, by clk_aux_p_o : out std_logic; -- going to CLK2 SMC on the front pannel, by
...@@ -119,8 +119,6 @@ entity scb_top_bare is ...@@ -119,8 +119,6 @@ entity scb_top_bare is
dac_main_data_o : out std_logic; dac_main_data_o : out std_logic;
-- WRS Low jitter daughterboard (db) external clock -- WRS Low jitter daughterboard (db) external clock
clk_ext_db_i : in std_logic;
ext_board_osc_freq_i : in std_logic_vector (2 downto 0); ext_board_osc_freq_i : in std_logic_vector (2 downto 0);
ext_board_detected_i : in std_logic; ext_board_detected_i : in std_logic;
...@@ -589,6 +587,7 @@ begin ...@@ -589,6 +587,7 @@ begin
U_RT_Subsystem : wrsw_rt_subsystem U_RT_Subsystem : wrsw_rt_subsystem
generic map ( generic map (
g_num_rx_clocks => c_NUM_PORTS, g_num_rx_clocks => c_NUM_PORTS,
g_num_ext_clks => 2,
g_simulation => g_simulation) g_simulation => g_simulation)
port map ( port map (
clk_ref_i => clk_ref_i, clk_ref_i => clk_ref_i,
...@@ -597,7 +596,6 @@ begin ...@@ -597,7 +596,6 @@ begin
clk_rx_i => clk_rx_vec, clk_rx_i => clk_rx_vec,
clk_ext_i => pll_status_i, -- FIXME: UGLY HACK clk_ext_i => pll_status_i, -- FIXME: UGLY HACK
clk_ext_mul_i => clk_ext_mul_i, clk_ext_mul_i => clk_ext_mul_i,
clk_ext_db_i => clk_ext_db_i,
ext_board_detected_i => ext_board_detected_i, ext_board_detected_i => ext_board_detected_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i, clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_aux_p_o => clk_aux_p_o, clk_aux_p_o => clk_aux_p_o,
......
top/bare_top/wrsw_components_pkg.vhd
View file @ 8d17a35c
...@@ -206,14 +206,16 @@ package wrsw_components_pkg is ...@@ -206,14 +206,16 @@ package wrsw_components_pkg is
component wrsw_rt_subsystem component wrsw_rt_subsystem
generic ( generic (
g_num_rx_clocks : integer); g_num_rx_clocks : integer;
g_num_ext_clks : integer;
g_simulation : boolean);
port ( port (
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic; clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0); clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_aux_i : in std_logic; clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic; clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_ext_mul_locked_i: in std_logic; clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic; clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic; clk_aux_n_o : out std_logic;
...@@ -224,7 +226,6 @@ package wrsw_components_pkg is ...@@ -224,7 +226,6 @@ package wrsw_components_pkg is
rst_dmtd_n_i : in std_logic; rst_dmtd_n_i : in std_logic;
rst_periph_ref_n_i : in std_logic; rst_periph_ref_n_i : in std_logic;
rst_n_o : out std_logic; rst_n_o : out std_logic;
clk_ext_db_i : in std_logic;
wb_i : in t_wishbone_slave_in; wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out; wb_o : out t_wishbone_slave_out;
dac_helper_sync_n_o : out std_logic; dac_helper_sync_n_o : out std_logic;
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 8d17a35c
...@@ -207,6 +207,7 @@ package wrsw_top_pkg is ...@@ -207,6 +207,7 @@ package wrsw_top_pkg is
component wrsw_rt_subsystem component wrsw_rt_subsystem
generic ( generic (
g_num_rx_clocks : integer; g_num_rx_clocks : integer;
g_num_ext_clks : integer;
g_simulation : boolean); g_simulation : boolean);
port ( port (
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
...@@ -214,9 +215,8 @@ package wrsw_top_pkg is ...@@ -214,9 +215,8 @@ package wrsw_top_pkg is
clk_dmtd_i : in std_logic; clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0); clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_i : in std_logic; clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic; clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_ext_mul_locked_i: in std_logic; clk_ext_mul_locked_i: in std_logic;
clk_ext_db_i : in std_logic;
clk_aux_p_o : out std_logic; clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic; clk_aux_n_o : out std_logic;
clk_500_o : out std_logic; clk_500_o : out std_logic;
...@@ -302,8 +302,7 @@ package wrsw_top_pkg is ...@@ -302,8 +302,7 @@ package wrsw_top_pkg is
clk_dmtd_i : in std_logic; clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic; clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic := '0'; clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic := '0'; clk_ext_mul_locked_i : in std_logic_vector(1 downto 0) := (others=>'0');
clk_ext_db_i : in std_logic := '0';
ext_board_detected_i: in std_logic := '0'; ext_board_detected_i: in std_logic := '0';
clk_sys_o : out std_logic; clk_sys_o : out std_logic;
cpu_wb_i : in t_wishbone_slave_in; cpu_wb_i : in t_wishbone_slave_in;
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ 8d17a35c
...@@ -388,14 +388,14 @@ NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i; ...@@ -388,14 +388,14 @@ NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%; TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
# Avoid noisy DFFs near DMTD demodulation DFF # Avoid noisy DFFs near DMTD demodulation DFF
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d0" LOC = SLICE_X1Y22; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d1" LOC = SLICE_X1Y22; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" LOC = SLICE_X1Y22;
#CONFIG PROHIBIT = SLICE_X2Y19:SLICE_X5Y24; #CONFIG PROHIBIT = SLICE_X2Y19:SLICE_X5Y24;
#CONFIG PROHIBIT = SLICE_X0Y23:SLICE_X1Y24; #CONFIG PROHIBIT = SLICE_X0Y23:SLICE_X1Y24;
#CONFIG PROHIBIT = SLICE_X0Y19:SLICE_X1Y21; #CONFIG PROHIBIT = SLICE_X0Y19:SLICE_X1Y21;
#CONFIG PROHIBIT = SLICE_X0Y22; #CONFIG PROHIBIT = SLICE_X0Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2"; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2"; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24; AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9; AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4; AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4;
......
top/scb_18ports/scb_top_synthesis.vhd
View file @ 8d17a35c
...@@ -337,6 +337,7 @@ architecture Behavioral of scb_top_synthesis is ...@@ -337,6 +337,7 @@ architecture Behavioral of scb_top_synthesis is
signal local_reset, ext_pll_reset : std_logic; signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic; signal clk_ext, clk_ext_mul : std_logic;
signal clk_ext_mul_vec : std_logic_vector(1 downto 0);
signal clk_ext_100 : std_logic; signal clk_ext_100 : std_logic;
signal ext_pll_100_locked, ext_pll_62_locked : std_logic; signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
signal clk_ext_mul_locked : std_logic; signal clk_ext_mul_locked : std_logic;
...@@ -367,9 +368,8 @@ architecture Behavioral of scb_top_synthesis is ...@@ -367,9 +368,8 @@ architecture Behavioral of scb_top_synthesis is
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic; clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic; clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic; clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i: in std_logic; clk_ext_mul_locked_i: in std_logic;
clk_ext_db_i : in std_logic;
clk_aux_p_o : out std_logic; clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic; clk_aux_n_o : out std_logic;
clk_500_o : out std_logic; clk_500_o : out std_logic;
...@@ -672,6 +672,8 @@ begin ...@@ -672,6 +672,8 @@ begin
locked_o => ext_pll_62_locked); locked_o => ext_pll_62_locked);
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked; clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
clk_ext_mul_vec(0) <= clk_ext_mul;
clk_ext_mul_vec(1) <= ext_clk_62mhz_bufr;
-- Detect the external board (WRS Low jitter daughterboard) -- Detect the external board (WRS Low jitter daughterboard)
ext_board_checker_inst : wrsw_ext_board_check ext_board_checker_inst : wrsw_ext_board_check
...@@ -850,9 +852,8 @@ begin ...@@ -850,9 +852,8 @@ begin
clk_dmtd_i => clk_dmtd, clk_dmtd_i => clk_dmtd,
clk_sys_o => clk_sys, clk_sys_o => clk_sys,
clk_aux_i => clk_aux, clk_aux_i => clk_aux,
clk_ext_mul_i => clk_ext_mul, clk_ext_mul_i => clk_ext_mul_vec,
clk_ext_mul_locked_i=> clk_ext_mul_locked, clk_ext_mul_locked_i=> clk_ext_mul_locked,
clk_ext_db_i => ext_clk_62mhz_bufr,
clk_aux_p_o => clk_aux_p_o, clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o, clk_aux_n_o => clk_aux_n_o,
cpu_wb_i => top_master_out, cpu_wb_i => top_master_out,
......
top/scb_8ports/scb_top_synthesis.ucf
View file @ 8d17a35c
...@@ -46,7 +46,6 @@ NET "ext_board_loopback_o" LOC = AL30; ...@@ -46,7 +46,6 @@ NET "ext_board_loopback_o" LOC = AL30;
#NET "spll_dbg_o<3>" LOC=AM32; #NET "spll_dbg_o<3>" LOC=AM32;
#NET "spll_dbg_o<4>" LOC=AN32; #NET "spll_dbg_o<4>" LOC=AN32;
#NET "spll_dbg_o<5>" LOC=AP33; #NET "spll_dbg_o<5>" LOC=AP33;
#EBI BUS #EBI BUS
#NET "cpu_clk_i" LOC=""; #NET "cpu_clk_i" LOC="";
NET "cpu_cs_n_i" LOC="H34"; NET "cpu_cs_n_i" LOC="H34";
...@@ -155,16 +154,12 @@ NET "clk_sel_o" LOC="AK17"; ...@@ -155,16 +154,12 @@ NET "clk_sel_o" LOC="AK17";
### GTX PORTS - reversed to match MB port ordering ### ### GTX PORTS - reversed to match MB port ordering ###
#NET "gtx0_3_clk_n_i" LOC="AK5"; #NET "gtx0_3_clk_n_i" LOC="AK5";
#NET "gtx0_3_clk_p_i" LOC="AK6"; #NET "gtx0_3_clk_p_i" LOC="AK6";
#NET "gtx0_3_clk_n_i" IOSTANDARD="LVPECL_25"; #NET "gtx0_3_clk_n_i" IOSTANDARD="LVPECL_25";
#NET "gtx0_3_clk_p_i" IOSTANDARD="LVPECL_25"; #NET "gtx0_3_clk_p_i" IOSTANDARD="LVPECL_25";
#NET "gtx4_7_clk_n_i" LOC="AD5"; #NET "gtx4_7_clk_n_i" LOC="AD5";
#NET "gtx4_7_clk_p_i" LOC="AD6"; #NET "gtx4_7_clk_p_i" LOC="AD6";
#NET "gtx4_7_clk_n_i" IOSTANDARD="LVPECL_25"; #NET "gtx4_7_clk_n_i" IOSTANDARD="LVPECL_25";
#NET "gtx4_7_clk_p_i" IOSTANDARD="LVPECL_25"; #NET "gtx4_7_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx8_11_clk_n_i" LOC="V5"; NET "gtx8_11_clk_n_i" LOC="V5";
NET "gtx8_11_clk_p_i" LOC="V6"; NET "gtx8_11_clk_p_i" LOC="V6";
...@@ -186,64 +181,44 @@ NET "gtx16_19_clk_p_i" IOSTANDARD="LVPECL_25"; ...@@ -186,64 +181,44 @@ NET "gtx16_19_clk_p_i" IOSTANDARD="LVPECL_25";
#NET "gtx_rxp_i[0]" LOC="AP5"; # gtx0 #NET "gtx_rxp_i[0]" LOC="AP5"; # gtx0
#NET "gtx_rxn_i[0]" LOC="AP6"; #NET "gtx_rxn_i[0]" LOC="AP6";
#NET "gtx_txp_o[0]" LOC="AP1"; #NET "gtx_txp_o[0]" LOC="AP1";
#NET "gtx_txn_o[0]" LOC="AP2"; #NET "gtx_txn_o[0]" LOC="AP2";
#NET "gtx_rxp_i[1]" LOC="AM5"; # gtx1 #NET "gtx_rxp_i[1]" LOC="AM5"; # gtx1
#NET "gtx_rxn_i[1]" LOC="AM6"; #NET "gtx_rxn_i[1]" LOC="AM6";
#NET "gtx_txp_o[1]" LOC="AN3"; #NET "gtx_txp_o[1]" LOC="AN3";
#NET "gtx_txn_o[1]" LOC="AN4"; #NET "gtx_txn_o[1]" LOC="AN4";
#NET "gtx_rxp_i[2]" LOC="AL3"; # gtx2 #NET "gtx_rxp_i[2]" LOC="AL3"; # gtx2
#NET "gtx_rxn_i[2]" LOC="AL4"; #NET "gtx_rxn_i[2]" LOC="AL4";
#NET "gtx_txp_o[2]" LOC="AM1"; #NET "gtx_txp_o[2]" LOC="AM1";
#NET "gtx_txn_o[2]" LOC="AM2"; #NET "gtx_txn_o[2]" LOC="AM2";
#NET "gtx_rxp_i[3]" LOC="AJ3"; #NET "gtx_rxp_i[3]" LOC="AJ3";
#NET "gtx_rxn_i[3]" LOC="AJ4"; #NET "gtx_rxn_i[3]" LOC="AJ4";
#NET "gtx_txp_o[3]" LOC="AK1"; #NET "gtx_txp_o[3]" LOC="AK1";
#NET "gtx_txn_o[3]" LOC="AK2"; #NET "gtx_txn_o[3]" LOC="AK2";
#NET "gtx_rxp_i[4]" LOC="AG3"; #NET "gtx_rxp_i[4]" LOC="AG3";
#NET "gtx_rxn_i[4]" LOC="AG4"; #NET "gtx_rxn_i[4]" LOC="AG4";
#NET "gtx_txp_o[4]" LOC="AH1"; #NET "gtx_txp_o[4]" LOC="AH1";
#NET "gtx_txn_o[4]" LOC="AH2"; #NET "gtx_txn_o[4]" LOC="AH2";
#NET "gtx_rxp_i[5]" LOC="AF5"; #NET "gtx_rxp_i[5]" LOC="AF5";
#NET "gtx_rxn_i[5]" LOC="AF6"; #NET "gtx_rxn_i[5]" LOC="AF6";
#NET "gtx_txp_o[5]" LOC="AF1"; #NET "gtx_txp_o[5]" LOC="AF1";
#NET "gtx_txn_o[5]" LOC="AF2"; #NET "gtx_txn_o[5]" LOC="AF2";
#NET "gtx_rxp_i[6]" LOC="AE3"; #NET "gtx_rxp_i[6]" LOC="AE3";
#NET "gtx_rxn_i[6]" LOC="AE4"; #NET "gtx_rxn_i[6]" LOC="AE4";
#NET "gtx_txp_o[6]" LOC="AD1"; #NET "gtx_txp_o[6]" LOC="AD1";
#NET "gtx_txn_o[6]" LOC="AD2"; #NET "gtx_txn_o[6]" LOC="AD2";
#NET "gtx_rxp_i[7]" LOC="AC3"; #NET "gtx_rxp_i[7]" LOC="AC3";
#NET "gtx_rxn_i[7]" LOC="AC4"; #NET "gtx_rxn_i[7]" LOC="AC4";
#NET "gtx_txp_o[7]" LOC="AB1"; #NET "gtx_txp_o[7]" LOC="AB1";
#NET "gtx_txn_o[7]" LOC="AB2"; #NET "gtx_txn_o[7]" LOC="AB2";
#NET "gtx_rxp_i[8]" LOC="AA3"; #NET "gtx_rxp_i[8]" LOC="AA3";
#NET "gtx_rxn_i[8]" LOC="AA4"; #NET "gtx_rxn_i[8]" LOC="AA4";
#NET "gtx_txp_o[8]" LOC="Y1"; #NET "gtx_txp_o[8]" LOC="Y1";
#NET "gtx_txn_o[8]" LOC="Y2"; #NET "gtx_txn_o[8]" LOC="Y2";
#NET "gtx_rxp_i[9]" LOC="W3"; #NET "gtx_rxp_i[9]" LOC="W3";
#NET "gtx_rxn_i[9]" LOC="W4"; #NET "gtx_rxn_i[9]" LOC="W4";
#NET "gtx_txp_o[9]" LOC="V1"; #NET "gtx_txp_o[9]" LOC="V1";
#NET "gtx_txn_o[9]" LOC="V2"; #NET "gtx_txn_o[9]" LOC="V2";
NET "gtx_rxp_i[7]" LOC="U3"; NET "gtx_rxp_i[7]" LOC="U3";
NET "gtx_rxn_i[7]" LOC="U4"; NET "gtx_rxn_i[7]" LOC="U4";
...@@ -341,7 +316,6 @@ NET "ext_clk_10mhz_n_i" TNM_NET = "ext_clk_10mhz_n_i"; ...@@ -341,7 +316,6 @@ NET "ext_clk_10mhz_n_i" TNM_NET = "ext_clk_10mhz_n_i";
TIMESPEC TS_ext_clk_10mhz_n_i = PERIOD "ext_clk_10mhz_n_i" 100 ns HIGH 50 %; TIMESPEC TS_ext_clk_10mhz_n_i = PERIOD "ext_clk_10mhz_n_i" 100 ns HIGH 50 %;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19 #Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19
#NET "gen_phys[0].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].U_PHY/rx_rec_clk_bufin; #NET "gen_phys[0].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_0__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[0].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; #TIMESPEC TS_gen_phys_0__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[0].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[1].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[1].U_PHY/rx_rec_clk_bufin; #NET "gen_phys[1].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[1].U_PHY/rx_rec_clk_bufin;
...@@ -350,7 +324,6 @@ TIMESPEC TS_ext_clk_10mhz_n_i = PERIOD "ext_clk_10mhz_n_i" 100 ns HIGH 50 %; ...@@ -350,7 +324,6 @@ TIMESPEC TS_ext_clk_10mhz_n_i = PERIOD "ext_clk_10mhz_n_i" 100 ns HIGH 50 %;
#TIMESPEC TS_gen_phys_2__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[2].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; #TIMESPEC TS_gen_phys_2__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[2].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[3].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[3].U_PHY/rx_rec_clk_bufin; #NET "gen_phys[3].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[3].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_3__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[3].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; #TIMESPEC TS_gen_phys_3__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[3].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[4].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].U_PHY/rx_rec_clk_bufin; #NET "gen_phys[4].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_4__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; #TIMESPEC TS_gen_phys_4__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[4].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[4].U_PHY/tx_out_clk_bufin; #NET "gen_phys[4].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[4].U_PHY/tx_out_clk_bufin;
...@@ -385,12 +358,10 @@ TIMESPEC TS_gen_phys_8__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[8].U_PHY/rx_re ...@@ -385,12 +358,10 @@ TIMESPEC TS_gen_phys_8__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[8].U_PHY/rx_re
#TIMESPEC TS_gen_phys_16__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[16].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%; #TIMESPEC TS_gen_phys_16__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[16].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[17].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[17].U_PHY/rx_rec_clk_bufin; #NET "gen_phys[17].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[17].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_17__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[17].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; #TIMESPEC TS_gen_phys_17__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[17].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gtx0_3_clk_n_i" TNM_NET = gtx0_3_clk_n_i; #NET "gtx0_3_clk_n_i" TNM_NET = gtx0_3_clk_n_i;
#TIMESPEC TS_gtx0_3_clk_n_i = PERIOD "gtx0_3_clk_n_i" 8 ns HIGH 50%; #TIMESPEC TS_gtx0_3_clk_n_i = PERIOD "gtx0_3_clk_n_i" 8 ns HIGH 50%;
#NET "gtx0_3_clk_p_i" TNM_NET = gtx0_3_clk_p_i; #NET "gtx0_3_clk_p_i" TNM_NET = gtx0_3_clk_p_i;
#TIMESPEC TS_gtx0_3_clk_p_i = PERIOD "gtx0_3_clk_p_i" 8 ns HIGH 50%; #TIMESPEC TS_gtx0_3_clk_p_i = PERIOD "gtx0_3_clk_p_i" 8 ns HIGH 50%;
#NET "gtx4_7_clk_n_i" TNM_NET = gtx4_7_clk_n_i; #NET "gtx4_7_clk_n_i" TNM_NET = gtx4_7_clk_n_i;
#TIMESPEC TS_gtx4_7_clk_n_i = PERIOD "gtx4_7_clk_n_i" 8 ns HIGH 50%; #TIMESPEC TS_gtx4_7_clk_n_i = PERIOD "gtx4_7_clk_n_i" 8 ns HIGH 50%;
#NET "gtx4_7_clk_p_i" TNM_NET = gtx4_7_clk_p_i; #NET "gtx4_7_clk_p_i" TNM_NET = gtx4_7_clk_p_i;
...@@ -409,21 +380,20 @@ NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i; ...@@ -409,21 +380,20 @@ NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%; TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
# Avoid noisy DFFs near DMTD demodulation DFF # Avoid noisy DFFs near DMTD demodulation DFF
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d0" LOC = SLICE_X1Y22; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d1" LOC = SLICE_X1Y22; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" LOC = SLICE_X1Y22;
#CONFIG PROHIBIT = SLICE_X2Y19:SLICE_X5Y24; #CONFIG PROHIBIT = SLICE_X2Y19:SLICE_X5Y24;
#CONFIG PROHIBIT = SLICE_X0Y23:SLICE_X1Y24; #CONFIG PROHIBIT = SLICE_X0Y23:SLICE_X1Y24;
#CONFIG PROHIBIT = SLICE_X0Y19:SLICE_X1Y21; #CONFIG PROHIBIT = SLICE_X0Y19:SLICE_X1Y21;
#CONFIG PROHIBIT = SLICE_X0Y22; #CONFIG PROHIBIT = SLICE_X0Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2"; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.gen_with_ext_daughterboard.U_DMTD_EXT_daughterboard/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2"; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24; AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9; AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4; AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4;
AREA_GROUP "pblock_ext_dmtd_2" GROUP=CLOSED; AREA_GROUP "pblock_ext_dmtd_2" GROUP=CLOSED;
AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED; AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;
#NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE; #NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17 #Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17
TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY; TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY; TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY;
top/scb_8ports/scb_top_synthesis.vhd
View file @ 8d17a35c
...@@ -337,6 +337,7 @@ architecture Behavioral of scb_top_synthesis is ...@@ -337,6 +337,7 @@ architecture Behavioral of scb_top_synthesis is
signal local_reset, ext_pll_reset : std_logic; signal local_reset, ext_pll_reset : std_logic;
signal clk_ext, clk_ext_mul : std_logic; signal clk_ext, clk_ext_mul : std_logic;
signal clk_ext_mul_vec : std_logic_vector(1 downto 0);
signal clk_ext_100 : std_logic; signal clk_ext_100 : std_logic;
signal ext_pll_100_locked, ext_pll_62_locked : std_logic; signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
signal clk_ext_mul_locked : std_logic; signal clk_ext_mul_locked : std_logic;
...@@ -366,9 +367,8 @@ architecture Behavioral of scb_top_synthesis is ...@@ -366,9 +367,8 @@ architecture Behavioral of scb_top_synthesis is
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic; clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic; clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic; clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i: in std_logic; clk_ext_mul_locked_i: in std_logic;
clk_ext_db_i : in std_logic;
clk_aux_p_o : out std_logic; clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic; clk_aux_n_o : out std_logic;
clk_500_o : out std_logic; clk_500_o : out std_logic;
...@@ -680,6 +680,8 @@ begin ...@@ -680,6 +680,8 @@ begin
locked_o => ext_pll_62_locked); locked_o => ext_pll_62_locked);
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked; clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
clk_ext_mul_vec(0) <= clk_ext_mul;
clk_ext_mul_vec(1) <= ext_clk_62mhz;
--dbg_clk_ext_o <= clk_ext_mul; --dbg_clk_ext_o <= clk_ext_mul;
local_reset <= not sys_rst_n_i; local_reset <= not sys_rst_n_i;
...@@ -848,9 +850,8 @@ begin ...@@ -848,9 +850,8 @@ begin
clk_dmtd_i => clk_dmtd, clk_dmtd_i => clk_dmtd,
clk_sys_o => clk_sys, clk_sys_o => clk_sys,
clk_aux_i => clk_aux, clk_aux_i => clk_aux,
clk_ext_mul_i => clk_ext_mul, clk_ext_mul_i => clk_ext_mul_vec,
clk_ext_mul_locked_i=> clk_ext_mul_locked, clk_ext_mul_locked_i=> clk_ext_mul_locked,
clk_ext_db_i => ext_clk_62mhz,
clk_aux_p_o => clk_aux_p_o, clk_aux_p_o => clk_aux_p_o,
clk_aux_n_o => clk_aux_n_o, clk_aux_n_o => clk_aux_n_o,
-- clk_500_o => clk_500_o, -- clk_500_o => clk_500_o,
......
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