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White Rabbit Switch - Gateware
Commit 907ad8dc authored by Maciej Lipinski's avatar Maciej Lipinski
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[RTU/FastMatch] added chipscope to debug Fast Match bug

parent be12a9c2
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Showing with 59 additions and 4 deletions
modules/wrsw_rtu/rtu_fast_match.vhd
View file @ 907ad8dc
......@@ -144,7 +144,12 @@ architecture behavioral of rtu_fast_match is
signal traffic_hp_d : std_logic;
signal rtu_pcr_nonvlan_drop_at_ingress : std_logic_vector(c_rtu_max_ports -1 downto 0);
signal vtab_rd_addr : std_logic_vector(c_wrsw_vid_width-1 downto 0);
signal CONTROL0 : std_logic_vector(35 downto 0);
signal TRIG0, TRIG1, TRIG2, TRIG3 : std_logic_vector(31 downto 0);
constant match_rsp_zero : t_match_response := (
valid => '0',
port_mask => (others => '0'),
......@@ -162,6 +167,21 @@ architecture behavioral of rtu_fast_match is
fid => (others =>'0'),
port_mask => (others =>'0'));
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
end component;
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
begin
zeros <= (others => '0');
......@@ -279,7 +299,7 @@ begin
vtab_rd_entry_d <= vlan_tab_entry_zero;
vtab_rd_addr_o <= (others =>'0');
vtab_rd_addr <= (others =>'0');
else
......@@ -292,11 +312,11 @@ begin
--------------------------------------------------------------------------------------
if(unsigned(grant) /= 0) then
-- VLAN access
vtab_rd_addr_o <= rtu_req_stage_g.vid;
vtab_rd_addr <= rtu_req_stage_g.vid;
pipeline_grant(0) <= grant;
pipeline_valid(0) <= '1';
else
--vtab_rd_addr_o <= (others => '0'); -- remember address as at some point we read
vtab_rd_addr <= (others => '0'); -- remember address as at some point we read
-- data from VID=0, i.e. drop
pipeline_grant(0) <= (others => '0');
pipeline_valid(0) <= '0';
......@@ -306,10 +326,16 @@ begin
-- register for stage 1: VLAN entry in
--------------------------------------------------------------------------------------
if(unsigned(pipeline_grant(0)) /= 0) then
-- test
-- vtab_rd_addr <= rtu_req_stage_0.vid;
rtu_req_stage_0_prio_d <= rtu_req_stage_0.prio;
rtu_req_stage_0_dmac_d <= rtu_req_stage_0.dmac;
rtu_req_stage_0_has_prio_d <= rtu_req_stage_0.has_prio ;
else
-- test
-- vtab_rd_addr <= (others => '0');
rtu_req_stage_0_prio_d <= (others =>'0');
rtu_req_stage_0_dmac_d <= (others =>'0');
rtu_req_stage_0_has_prio_d <= '0';
......@@ -416,5 +442,34 @@ begin
pipeline_match_rsp(1).hp;
match_rsp_valid_o <= pipeline_grant(3) when (tru_enabled_i = '0') else
pipeline_grant(4);
vtab_rd_addr_o <= vtab_rd_addr;
CS_ICON : chipscope_icon
port map (
CONTROL0 => CONTROL0);
CS_ILA : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => clk_i,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2,
TRIG3 => TRIG3);
TRIG0(11 downto 0) <= vtab_rd_addr;
TRIG0(14 downto 12) <= vtab_rd_entry_i.prio;
TRIG0(17 downto 15) <= rsp_fast_match.prio;
TRIG0( 22) <= vtab_rd_entry_i.drop;
TRIG0( 23) <= rsp_fast_match.drop;
TRIG0(31 downto 24) <= vtab_rd_entry_i.fid;
TRIG1(15 downto 0) <= vtab_rd_entry_i.port_mask(15 downto 0);
TRIG1(31 downto 16) <= rsp_fast_match.port_mask(15 downto 0);
TRIG2(1*8-1 downto 0*8) <= pipeline_grant(0);
TRIG2(2*8-1 downto 1*8) <= pipeline_grant(1);
TRIG2(3*8-1 downto 2*8) <= pipeline_grant(2);
TRIG2(4*8-1 downto 3*8) <= pipeline_grant(3);
TRIG3(1*8-1 downto 0*8) <= pipeline_grant(4);
TRIG3(31 downto 16) <= vtab_rd_entry_d.port_mask(15 downto 0);
end architecture;
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