added initial build scripts for wrsv4 bringup

9a3b3c9f · Harvey Leicester · 90c522d1 · 9a3b3c9f · 9a3b3c9f · 9a3b3c9f
Commit 9a3b3c9f authored Mar 20, 2024 by Harvey Leicester
5 changed files
--- a/syn/wrsv4_bringup/build.tcl
+++ b/syn/wrsv4_bringup/build.tcl
+set origin_dir [exec pwd]
+set fpga_part "xczu17eg-ffvc1760-1-e"
+set top_target "wrsv4_bringup"
+set top_dir "$origin_dir/../../top/wrsv4_bringup"
+set top_src $top_dir/${top_target}_top.vhd 
+set top_xdc "${top_dir}/constraints.xdc"
+set bd_tcl "ps_bd.tcl"
+set build_dir "$origin_dir/build"
+set report_dir "$build_dir/reports"
+set dcp_dir "$build_dir/dcp"
+set xilinx_dir "$build_dir/xilinx"
+
+# Create 'sources_1' fileset (if not found)
+#if {[string equal [get_filesets -quiet sources_1] ""]} {
+#  create_fileset -srcset sources_1
+#}
+
+file mkdir $build_dir
+file mkdir $report_dir
+file mkdir $dcp_dir
+file mkdir $xilinx_dir
+
+source files.tcl
+
+foreach hdl_src [list $files_vhdl] {
+	puts "building $hdl_src\n"
+	read_vhdl $hdl_src
+}
+
+foreach hdl_src [list $files_verilog] {
+	puts "building $hdl_src\n"
+	read_verilog $hdl_src
+}
+
+#not used with ibert
+# foreach xdc_src [list $files_xdc] {
+# 	puts "building $xdc_src\n"
+# 	read_xdc $xdc_src
+# }
+
+cd $xilinx_dir
+
+#ibert ip 
+source ${origin_dir}/ibert_ultrascale_gth_0.tcl
+generate_target all [get_files "${xilinx_dir}/.srcs/sources_1/ip/ibert_ultrascale_gth_0/ibert_ultrascale_gth_0.xci"]
+create_ip_run [get_files -of_objects [get_fileset sources_1] "${xilinx_dir}/.srcs/sources_1/ip/ibert_ultrascale_gth_0/ibert_ultrascale_gth_0.xci"]
+synth_ip [get_ips ibert_ultrascale_gth_0] -force
+
+#regenerate the ps block design
+source ${origin_dir}/$bd_tcl
+
+#generate hdl wrapper
+update_compile_order -fileset sources_1
+set_property target_language VHDL [current_project]
+make_wrapper -files [get_files "${xilinx_dir}/.srcs/sources_1/bd/ps/ps.bd"] -top
+
+#read generated wrapper into default lib
+read_vhdl "${xilinx_dir}/.gen/sources_1/bd/ps/hdl/ps_wrapper.vhd"
+#generate output products
+generate_target all [get_files "${xilinx_dir}/.srcs/sources_1/bd/ps/ps.bd"]
+
+cd $build_dir
+
+#top level 
+read_vhdl $top_src
+read_xdc $top_xdc
+
+#run synthesis
+synth_design -top $top_target -part $fpga_part
+write_checkpoint -force $dcp_dir/post_syn 
+report_timing_summary -file $report_dir/post_synth_timing_summary.rpt
+report_utilization -hierarchical -hierarchical_depth 5 -file $report_dir/post_synth_util.rpt
+
+#add debug cores
+#read_xdc ${origin_dir}/debug.xdc 
+
+#implementation
+opt_design
+#power_opt_design
+place_design
+report_clock_utilization -file $report_dir/clock_util.rpt
+phys_opt_design
+write_checkpoint -force $dcp_dir/post_place.dcp
+report_utilization -file $report_dir/post_place_util.rpt
+report_timing_summary -file $report_dir/post_place_timing_summary.rpt
+route_design
+write_checkpoint -force $dcp_dir/post_route.dcp
+report_route_status -file $report_dir/post_route_status.rpt
+report_timing_summary -file $report_dir/post_route_timing_summary.rpt
+report_power -file $report_dir/post_route_power.rpt
+report_drc -file $report_dir/post_imp_drc.rpt
+write_vhdl -force $dcp_dir/cpu_impl_netlist.vhd
+
+write_bitstream -verbose -force $build_dir/$top_target.bit
--- a/syn/wrsv4_bringup/build_bitstream.sh
+++ b/syn/wrsv4_bringup/build_bitstream.sh
+#!/bin/bash
+
+source /tools/Xilinx/Vivado/2022.2/settings64.sh
+
+vivado -mode batch -source build.tcl
--- a/syn/wrsv4_bringup/files.tcl
+++ b/syn/wrsv4_bringup/files.tcl
--- a/syn/wrsv4_bringup/ibert_ultrascale_gth_0.tcl
+++ b/syn/wrsv4_bringup/ibert_ultrascale_gth_0.tcl
+set_part xczu17eg-ffvc1760-1-e
+
+set ibert_ultrascale_gth_0 [create_ip -name ibert_ultrascale_gth -vendor xilinx.com -library ip -version 1.4 -module_name ibert_ultrascale_gth_0]
+
+ set_property -dict [list \
+   CONFIG.C_ADD_RXOUTCLK_PROBES {false} \
+   CONFIG.C_PROTOCOL_COUNT {1} \
+   CONFIG.C_PROTOCOL_MAXLINERATE_1 {1.25} \
+   CONFIG.C_PROTOCOL_PLL_1 {QPLL0} \
+   CONFIG.C_PROTOCOL_QUAD0 {Custom_1_/_1.25_Gbps} \
+   CONFIG.C_PROTOCOL_QUAD1 {Custom_1_/_1.25_Gbps} \
+   CONFIG.C_PROTOCOL_QUAD2 {Custom_1_/_1.25_Gbps} \
+   CONFIG.C_PROTOCOL_QUAD3 {Custom_1_/_1.25_Gbps} \
+   CONFIG.C_PROTOCOL_QUAD4 {Custom_1_/_1.25_Gbps} \
+   CONFIG.C_PROTOCOL_QUAD5 {Custom_1_/_1.25_Gbps} \
+   CONFIG.C_PROTOCOL_QUAD6 {None} \
+   CONFIG.C_PROTOCOL_QUAD7 {None} \
+   CONFIG.C_PROTOCOL_QUAD_COUNT_1 {6} \
+   CONFIG.C_PROTOCOL_REFCLK_FREQUENCY_1 {125} \
+   CONFIG.C_REFCLK_SOURCE_QUAD_0 {MGTREFCLK0_224} \
+   CONFIG.C_REFCLK_SOURCE_QUAD_1 {MGTREFCLK0_225} \
+   CONFIG.C_REFCLK_SOURCE_QUAD_2 {MGTREFCLK0_226} \
+   CONFIG.C_REFCLK_SOURCE_QUAD_3 {MGTREFCLK0_227} \
+   CONFIG.C_REFCLK_SOURCE_QUAD_4 {MGTREFCLK0_228} \
+   CONFIG.C_REFCLK_SOURCE_QUAD_5 {MGTREFCLK0_229} \
+   CONFIG.C_REFCLK_SOURCE_QUAD_6 {None} \
+   CONFIG.C_REFCLK_SOURCE_QUAD_7 {None} \
+   CONFIG.C_SYSCLOCK_SOURCE_INT {QUAD224_0} \
+ ] [get_ips ibert_ultrascale_gth_0]
+
+# Runtime Parameters
+set_property -dict { 
+  GENERATE_SYNTH_CHECKPOINT {1}
+} $ibert_ultrascale_gth_0
+
--- a/syn/wrsv4_bringup/ps_bd.tcl
+++ b/syn/wrsv4_bringup/ps_bd.tcl