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Commit 9d6e16ed authored by Maciej Lipinski's avatar Maciej Lipinski
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RTU: added optional hack (can be turned on with generics) which was introduce to… 

RTU: added optional hack (can be turned on with generics) which was introduce to prevent Endpoint from pushing new requests to RTU while the current one is currently handled. This might cause errors in forwaring packets (RTU handling requets of packets which were dropped by Endpint because the buffer has become full waiting for decisions of RTU of the previous packets. Everythig because RTU is to slow .... (testing throwing bursts of frames at 14 ports simultaneusly). Also: added missing prioriy connection in the wrapper
parent b6be79f8
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modules/wrsw_rtu/xwrsw_rtu.vhd
View file @ 9d6e16ed
-------------------------------------------------------------------------------
-- Title : eXtended Routing Table Unit (RTU)
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wrsw_rtu.vhd
-- Authors : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2012-01-10
-- Last update: 2012-03-06
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description: With usable interface
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 Tomasz Wlostowski / CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-01-10 1.0 twlostow created
-- 2010-11-29 1.1 mlipinsk connected prio, added temp_hack
-------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.math_real.CEIL;
use ieee.math_real.log2;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.wrsw_shared_types_pkg.all; use work.wrsw_shared_types_pkg.all;
...@@ -10,6 +52,8 @@ entity xwrsw_rtu is ...@@ -10,6 +52,8 @@ entity xwrsw_rtu is
generic ( generic (
g_interface_mode : t_wishbone_interface_mode := PIPELINED; g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE; g_address_granularity : t_wishbone_address_granularity := BYTE;
g_handle_only_single_req_per_port : boolean := FALSE;
g_prio_num : integer;
g_num_ports : integer; g_num_ports : integer;
g_port_mask_bits : integer); g_port_mask_bits : integer);
...@@ -62,6 +106,8 @@ architecture wrapper of xwrsw_rtu is ...@@ -62,6 +106,8 @@ architecture wrapper of xwrsw_rtu is
wb_we_i : in std_logic); wb_we_i : in std_logic);
end component; end component;
constant c_prio_num_width : integer := integer(CEIL(LOG2(real(g_prio_num ))));
signal wb_in : t_wishbone_slave_in; signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out; signal wb_out : t_wishbone_slave_out;
...@@ -78,7 +124,9 @@ architecture wrapper of xwrsw_rtu is ...@@ -78,7 +124,9 @@ architecture wrapper of xwrsw_rtu is
signal rsp_drop : std_logic_vector(c_rtu_num_ports -1 downto 0); signal rsp_drop : std_logic_vector(c_rtu_num_ports -1 downto 0);
signal rsp_prio : std_logic_vector (c_rtu_num_ports * c_wrsw_prio_width-1 downto 0); signal rsp_prio : std_logic_vector (c_rtu_num_ports * c_wrsw_prio_width-1 downto 0);
signal rsp_ack : std_logic_vector(c_rtu_num_ports -1 downto 0); signal rsp_ack : std_logic_vector(c_rtu_num_ports -1 downto 0);
signal port_full_hacked : std_logic_vector(c_rtu_num_ports -1 downto 0);
signal port_full : std_logic_vector(c_rtu_num_ports -1 downto 0); signal port_full : std_logic_vector(c_rtu_num_ports -1 downto 0);
signal port_idle : std_logic_vector(c_rtu_num_ports -1 downto 0);
begin -- wrapper begin -- wrapper
...@@ -95,10 +143,42 @@ begin -- wrapper ...@@ -95,10 +143,42 @@ begin -- wrapper
rsp_o(i).port_mask(g_port_mask_bits-1 downto 0) <= rsp_dst_port_mask(c_wrsw_num_ports * i + g_port_mask_bits -1 downto c_wrsw_num_ports * i); rsp_o(i).port_mask(g_port_mask_bits-1 downto 0) <= rsp_dst_port_mask(c_wrsw_num_ports * i + g_port_mask_bits -1 downto c_wrsw_num_ports * i);
rsp_o(i).drop <= rsp_drop(i); rsp_o(i).drop <= rsp_drop(i);
rsp_ack(i) <= rsp_ack_i(i); rsp_ack(i) <= rsp_ack_i(i);
rsp_o(i).prio<=(others => '0'); rsp_o(i).prio <= rsp_prio(c_wrsw_prio_width*i + c_prio_num_width-1 downto c_wrsw_prio_width*i);
req_full_o(i) <= port_full(i); req_full_o(i) <= port_full_hacked(i) or port_full(i) or (not port_idle(i));
end generate gen_merge_signals; end generate gen_merge_signals;
-------------------------- TEMPORARY HACK -------------------------------------------------------
-- this was added because RTU is too slow !
-- with a full load (sending simultaneiusly burts of pcks on 14 ports, the RTU does not manage
-- to give resonse in a reasonable time. Thus, many requests are sent by Endpoint to RTU while
-- processing. Endpoint is stalled by SWcore wating for RTU's response. Endpoint's buffer finishes
-- and it drops pck, but this pck's request has already been sent to RTU and it's queued...
-- and at this point we have mess
-- TEMPORARY SOLUTION: we don't accept new requests from a given Endpoin while its request
-- is still processed by RTU. This will (should) cause pcks to be lost, but at least it will
-- not cause mess in the forwarding process.
gen_hack_t: if (g_handle_only_single_req_per_port = TRUE) generate
gen_force_full: for i in 0 to g_num_ports-1 generate
p_force_full: process(clk_sys_i) begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
port_full_hacked(i) <='0';
else
if rq_strobe_p(i) = '1' then
port_full_hacked(i) <='1';
elsif rsp_ack_i(i) ='1' then
port_full_hacked(i) <='0';
end if;
end if;
end if;
end process p_force_full;
end generate gen_force_full;
end generate gen_hack_t;
gen_hack_f: if (g_handle_only_single_req_per_port = FALSE) generate
port_full_hacked <= (others => '0');
end generate gen_hack_f;
--------------------------------------------------------------------------------------------------
gen_term_unused : for i in g_num_ports to c_rtu_num_ports-1 generate gen_term_unused : for i in g_num_ports to c_rtu_num_ports-1 generate
rq_strobe_p(i) <= '0'; rq_strobe_p(i) <= '0';
...@@ -130,7 +210,7 @@ begin -- wrapper ...@@ -130,7 +210,7 @@ begin -- wrapper
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
clk_match_i => clk_sys_i, clk_match_i => clk_sys_i,
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
rtu_idle_o => open, rtu_idle_o => port_idle,
rq_strobe_p_i => rq_strobe_p, rq_strobe_p_i => rq_strobe_p,
rq_smac_i => rq_smac, rq_smac_i => rq_smac,
rq_dmac_i => rq_dmac, rq_dmac_i => rq_dmac,
......
top/bare_top/wrsw_components_pkg.vhd
View file @ 9d6e16ed
...@@ -245,6 +245,8 @@ package wrsw_components_pkg is ...@@ -245,6 +245,8 @@ package wrsw_components_pkg is
generic ( generic (
g_interface_mode : t_wishbone_interface_mode; g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity; g_address_granularity : t_wishbone_address_granularity;
g_handle_only_single_req_per_port : boolean := FALSE;
g_prio_num : integer;
g_num_ports : integer; g_num_ports : integer;
g_port_mask_bits : integer); g_port_mask_bits : integer);
port ( port (
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 9d6e16ed
...@@ -289,6 +289,8 @@ package wrsw_top_pkg is ...@@ -289,6 +289,8 @@ package wrsw_top_pkg is
generic ( generic (
g_interface_mode : t_wishbone_interface_mode; g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity; g_address_granularity : t_wishbone_address_granularity;
g_handle_only_single_req_per_port : boolean := FALSE;
g_prio_num : integer;
g_num_ports : integer; g_num_ports : integer;
g_port_mask_bits : integer); g_port_mask_bits : integer);
port ( port (
......
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