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White Rabbit Switch - Gateware
Commit a155acb2 authored by Maciej Lipinski's avatar Maciej Lipinski
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LJ: Rename LJD to LJ, Low-Jitter functionality not specific only to the LJ Daughterboard 

The Low-Jitter functionality is now integrated on some versions of the
main board of the WRS. As such, we need to detect the LJ functionality
itself, not a board with it. Renamed from LJD to LJ for clarity.
parent 5062b008
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    modules/wrsw_rt_subsystem/Manifest.py
    View file @ a155acb2
    files = ["wrsw_rt_subsystem.vhd", "xwrsw_gen_10mhz.vhd", "gen10_wbgen2_pkg.vhd", files = ["wrsw_rt_subsystem.vhd", "xwrsw_gen_10mhz.vhd", "gen10_wbgen2_pkg.vhd",
    "gen10_wishbone_slave.vhd", "wrsw_ljd_detect.vhd"] "gen10_wishbone_slave.vhd", "wrsw_lj_detect.vhd"]
    modules/wrsw_rt_subsystem/wrsw_ljd_detect.vhd → modules/wrsw_rt_subsystem/wrsw_lj_detect.vhd
    View file @ a155acb2
    ------------------------------------------------------------------------------- -------------------------------------------------------------------------------
    -- Title : wrsw_ljd_detect -- Title : wrsw_lj_detect
    -- Project : White Rabbit Switch -- Project : White Rabbit Switch
    ------------------------------------------------------------------------------- -------------------------------------------------------------------------------
    -- File : wrsw_ljd_detect.vhd -- File : wrsw_lj_detect.vhd
    -- Author : Mattia Rzzi -- Author : Mattia Rzzi
    -- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
    -- Platform : FPGA-generic -- Platform : FPGA-generic
    -- Standard : VHDL -- Standard : VHDL
    ------------------------------------------------------------------------------- -------------------------------------------------------------------------------
    -- Description: -- Description:
    -- FSM to check the presence of the WRS Low jitter daughterboard -- FSM to check the presence of the WRS Low jitter (daughterboard) functionality.
    -- Initially, this module was used to detect the LJ daugtherboard, now it is
    -- used to detect the LJ functionality, whether integrated onto the main board,
    -- or provided on the plugged-in LJ daughterboard.
    ------------------------------------------------------------------------------- -------------------------------------------------------------------------------
    -- --
    -- Copyright (c) 2012 - 2016 CERN / BE-CO-HT -- Copyright (c) 2012 - 2016 CERN / BE-CO-HT
    ...@@ -45,7 +48,7 @@ use work.wrsw_top_pkg.all; ...@@ -45,7 +48,7 @@ use work.wrsw_top_pkg.all;
    library UNISIM; library UNISIM;
    use UNISIM.vcomponents.all; use UNISIM.vcomponents.all;
    entity wrsw_ljd_detect is entity wrsw_lj_detect is
    generic ( generic (
    g_pattern : std_logic_vector(63 downto 0) := x"CAFED00DCAFED00D"; g_pattern : std_logic_vector(63 downto 0) := x"CAFED00DCAFED00D";
    g_clk_divider : integer := 16); g_clk_divider : integer := 16);
    ...@@ -56,9 +59,9 @@ entity wrsw_ljd_detect is ...@@ -56,9 +59,9 @@ entity wrsw_ljd_detect is
    loopback_o : out std_logic; loopback_o : out std_logic;
    board_detected_o : out std_logic board_detected_o : out std_logic
    ); );
    end wrsw_ljd_detect; end wrsw_lj_detect;
    architecture Behavioral of wrsw_ljd_detect is architecture Behavioral of wrsw_lj_detect is
    signal clk_divider : integer range 0 to g_clk_divider-1; signal clk_divider : integer range 0 to g_clk_divider-1;
    signal clk_en : std_logic; signal clk_en : std_logic;
    ......
    modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
    View file @ a155acb2
    ...@@ -132,20 +132,20 @@ entity wrsw_rt_subsystem is ...@@ -132,20 +132,20 @@ entity wrsw_rt_subsystem is
    ------------------------------------------------------ ------------------------------------------------------
    -- WRS Low jitter daughterboard -- WRS Low jitter daughterboard
    ------------------------------------------------------ ------------------------------------------------------
    ljd_loopback_i : in std_logic := '0'; lj_loopback_i : in std_logic := '0';
    ljd_loopback_o : out std_logic; lj_loopback_o : out std_logic;
    ljd_clk1_en : out std_logic; lj_clk1_en : out std_logic;
    ljd_clk2_en : out std_logic; lj_clk2_en : out std_logic;
    ljd_detected_o : out std_logic; lj_detected_o : out std_logic;
    ljd_osc_freq_i : in std_logic_vector (2 downto 0) := (others=>'0'); lj_osc_freq_i : in std_logic_vector (2 downto 0) := (others=>'0');
    -- LJD AD9516 -- LJD AD9516
    ljd_pll_mosi_o : out std_logic; lj_pll_mosi_o : out std_logic;
    ljd_pll_miso_i : in std_logic; lj_pll_miso_i : in std_logic;
    ljd_pll_sck_o : out std_logic; lj_pll_sck_o : out std_logic;
    ljd_pll_cs_n_o : out std_logic; lj_pll_cs_n_o : out std_logic;
    ljd_pll_sync_n_o : out std_logic; lj_pll_sync_n_o : out std_logic;
    ljd_pll_reset_n_o : out std_logic; lj_pll_reset_n_o : out std_logic;
    ljd_pll_locked_i : in std_logic; lj_pll_locked_i : in std_logic;
    -- Debug -- Debug
    spll_dbg_o : out std_logic_vector(5 downto 0) spll_dbg_o : out std_logic_vector(5 downto 0)
    ...@@ -232,7 +232,7 @@ architecture rtl of wrsw_rt_subsystem is ...@@ -232,7 +232,7 @@ architecture rtl of wrsw_rt_subsystem is
    end if; end if;
    end f_pick; end f_pick;
    signal ljd_board_detected : std_logic; signal lj_board_detected : std_logic;
    signal ext_pll_locked : std_logic; signal ext_pll_locked : std_logic;
    signal ext_pll_reset : std_logic; signal ext_pll_reset : std_logic;
    ...@@ -428,10 +428,10 @@ begin -- rtl ...@@ -428,10 +428,10 @@ begin -- rtl
    slave_i => cnx_master_out(c_SLAVE_SPI_EXT), slave_i => cnx_master_out(c_SLAVE_SPI_EXT),
    slave_o => cnx_master_in(c_SLAVE_SPI_EXT), slave_o => cnx_master_in(c_SLAVE_SPI_EXT),
    desc_o => open, desc_o => open,
    pad_cs_o(0) => ljd_pll_cs_n_o, pad_cs_o(0) => lj_pll_cs_n_o,
    pad_sclk_o => ljd_pll_sck_o, pad_sclk_o => lj_pll_sck_o,
    pad_mosi_o => ljd_pll_mosi_o, pad_mosi_o => lj_pll_mosi_o,
    pad_miso_i => ljd_pll_miso_i); pad_miso_i => lj_pll_miso_i);
    U_GPIO : xwb_gpio_port U_GPIO : xwb_gpio_port
    generic map ( generic map (
    ...@@ -485,8 +485,8 @@ begin -- rtl ...@@ -485,8 +485,8 @@ begin -- rtl
    cpu_reset_n <= not gpio_out(2) and rst_sys_n_i; cpu_reset_n <= not gpio_out(2) and rst_sys_n_i;
    rst_n_o <= gpio_out(3); rst_n_o <= gpio_out(3);
    gpio_in(4) <= ljd_board_detected; gpio_in(4) <= lj_board_detected;
    gpio_in(7 downto 5) <= ljd_osc_freq_i; gpio_in(7 downto 5) <= lj_osc_freq_i;
    U_Main_DAC : gc_serial_dac U_Main_DAC : gc_serial_dac
    ...@@ -526,26 +526,26 @@ begin -- rtl ...@@ -526,26 +526,26 @@ begin -- rtl
    ------------------------------------------------------ ------------------------------------------------------
    -- WRS Low jitter daughterboard -- WRS Low jitter daughterboard
    ------------------------------------------------------ ------------------------------------------------------
    ljd_clk1_en <= '1'; lj_clk1_en <= '1';
    ljd_clk2_en <= '1'; lj_clk2_en <= '1';
    ljd_pll_sync_n_o <= '1'; lj_pll_sync_n_o <= '1';
    -- Detect the Low Jitter Daughterboard -- Detect the Low Jitter Daughterboard/functionality
    ljd_detect_inst : entity work.wrsw_ljd_detect lj_detect_inst : entity work.wrsw_lj_detect
    generic map ( generic map (
    g_clk_divider => 16, g_clk_divider => 16,
    g_pattern => x"CAFED00DCAFED00D") g_pattern => x"CAFED00DCAFED00D")
    port map ( port map (
    clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
    rst_n_i => rst_sys_n_i, rst_n_i => rst_sys_n_i,
    loopback_i => ljd_loopback_i, loopback_i => lj_loopback_i,
    loopback_o => ljd_loopback_o, loopback_o => lj_loopback_o,
    board_detected_o => ljd_board_detected); board_detected_o => lj_board_detected);
    ljd_detected_o <= ljd_board_detected; lj_detected_o <= lj_board_detected;
    ext_pll_locked <= ljd_pll_locked_i when(ljd_board_detected = '1') else ext_pll_locked <= lj_pll_locked_i when(lj_board_detected = '1') else
    clk_ext_mul_locked_i; clk_ext_mul_locked_i;
    ljd_pll_reset_n_o <= not ext_pll_reset when(ljd_board_detected = '1') else lj_pll_reset_n_o <= not ext_pll_reset when(lj_board_detected = '1') else
    '1'; '1';
    end rtl; end rtl;
    ......
    top/bare_top/scb_top_bare.vhd
    View file @ a155acb2
    ...@@ -136,25 +136,25 @@ entity scb_top_bare is ...@@ -136,25 +136,25 @@ entity scb_top_bare is
    ------------------------------------------------------------------------------- -------------------------------------------------------------------------------
    -- Low Jitter Daughterboard support -- Low Jitter Daughterboard support
    ------------------------------------------------------------------------------- -------------------------------------------------------------------------------
    ljd_dac_main_sync_n_o : out std_logic; lj_dac_main_sync_n_o : out std_logic;
    ljd_dac_main_sclk_o : out std_logic; lj_dac_main_sclk_o : out std_logic;
    ljd_dac_main_data_o : out std_logic; lj_dac_main_data_o : out std_logic;
    ljd_loopback_i : in std_logic; lj_loopback_i : in std_logic;
    ljd_loopback_o : out std_logic; lj_loopback_o : out std_logic;
    ljd_clk1_en : out std_logic; lj_clk1_en : out std_logic;
    ljd_clk2_en : out std_logic; lj_clk2_en : out std_logic;
    ljd_detected_o : out std_logic; lj_detected_o : out std_logic;
    ljd_present_o : out std_logic; lj_present_o : out std_logic;
    ljd_osc_freq_i : in std_logic_vector (2 downto 0); lj_osc_freq_i : in std_logic_vector (2 downto 0);
    -- LJD AD9516 -- LJD AD9516
    ljd_pll_mosi_o : out std_logic; lj_pll_mosi_o : out std_logic;
    ljd_pll_miso_i : in std_logic; lj_pll_miso_i : in std_logic;
    ljd_pll_sck_o : out std_logic; lj_pll_sck_o : out std_logic;
    ljd_pll_cs_n_o : out std_logic; lj_pll_cs_n_o : out std_logic;
    ljd_pll_sync_n_o : out std_logic; lj_pll_sync_n_o : out std_logic;
    ljd_pll_reset_n_o : out std_logic; lj_pll_reset_n_o : out std_logic;
    ljd_pll_locked_i : in std_logic; lj_pll_locked_i : in std_logic;
    ------------------------------------------------------------------------------- -------------------------------------------------------------------------------
    -- Misc pins -- Misc pins
    ...@@ -467,8 +467,8 @@ architecture rtl of scb_top_bare is ...@@ -467,8 +467,8 @@ architecture rtl of scb_top_bare is
    signal nic_rtu_rsp : t_rtu_response; signal nic_rtu_rsp : t_rtu_response;
    signal nic_rtu_ack : std_logic; signal nic_rtu_ack : std_logic;
    signal ljd_present : std_logic; signal lj_present : std_logic;
    signal ljd_detected : std_logic; signal lj_detected : std_logic;
    signal dac_main_sync_n : std_logic; signal dac_main_sync_n : std_logic;
    signal dac_main_sclk : std_logic; signal dac_main_sclk : std_logic;
    signal dac_main_data : std_logic; signal dac_main_data : std_logic;
    ...@@ -671,19 +671,19 @@ begin ...@@ -671,19 +671,19 @@ begin
    pll_sync_n_o => pll_sync_n_o, pll_sync_n_o => pll_sync_n_o,
    pll_reset_n_o => pll_reset_n_o, pll_reset_n_o => pll_reset_n_o,
    ljd_loopback_i => ljd_loopback_i, lj_loopback_i => lj_loopback_i,
    ljd_loopback_o => ljd_loopback_o, lj_loopback_o => lj_loopback_o,
    ljd_clk1_en => ljd_clk1_en, lj_clk1_en => lj_clk1_en,
    ljd_clk2_en => ljd_clk2_en, lj_clk2_en => lj_clk2_en,
    ljd_detected_o => ljd_detected, lj_detected_o => lj_detected,
    ljd_osc_freq_i => ljd_osc_freq_i, lj_osc_freq_i => lj_osc_freq_i,
    ljd_pll_mosi_o => ljd_pll_mosi_o, lj_pll_mosi_o => lj_pll_mosi_o,
    ljd_pll_miso_i => ljd_pll_miso_i, lj_pll_miso_i => lj_pll_miso_i,
    ljd_pll_sck_o => ljd_pll_sck_o, lj_pll_sck_o => lj_pll_sck_o,
    ljd_pll_cs_n_o => ljd_pll_cs_n_o, lj_pll_cs_n_o => lj_pll_cs_n_o,
    ljd_pll_sync_n_o => ljd_pll_sync_n_o, lj_pll_sync_n_o => lj_pll_sync_n_o,
    ljd_pll_reset_n_o => ljd_pll_reset_n_o, lj_pll_reset_n_o => lj_pll_reset_n_o,
    ljd_pll_locked_i => ljd_pll_locked_i, lj_pll_locked_i => lj_pll_locked_i,
    spll_dbg_o => spll_dbg_o); spll_dbg_o => spll_dbg_o);
    ...@@ -1334,27 +1334,27 @@ begin ...@@ -1334,27 +1334,27 @@ begin
    ------------------------------------------------------------------------------- -------------------------------------------------------------------------------
    -- WRS Low jitter daughterboard -- WRS Low jitter daughterboard
    ------------------------------------------------------------------------------- -------------------------------------------------------------------------------
    ljd_present <= '1' when ((ljd_detected='1') and (ljd_osc_freq_i/="111")) else '0'; lj_present <= '1' when ((lj_detected='1') and (lj_osc_freq_i/="111")) else '0';
    ljd_detected_o <= ljd_detected; lj_detected_o <= lj_detected;
    ljd_present_o <= ljd_present; lj_present_o <= lj_present;
    -- Redirect DAC output if external board detetected -- Redirect DAC output if external board detetected
    dac_redirection : process (ljd_present, dac_main_sync_n, dac_main_sclk, dac_main_data) dac_redirection : process (lj_present, dac_main_sync_n, dac_main_sclk, dac_main_data)
    begin begin
    if (ljd_present = '0') then if (lj_present = '0') then
    dac_main_sync_n_o <= dac_main_sync_n; dac_main_sync_n_o <= dac_main_sync_n;
    dac_main_sclk_o <= dac_main_sclk; dac_main_sclk_o <= dac_main_sclk;
    dac_main_data_o <= dac_main_data; dac_main_data_o <= dac_main_data;
    ljd_dac_main_sync_n_o <= '0'; lj_dac_main_sync_n_o <= '0';
    ljd_dac_main_sclk_o <= '0'; lj_dac_main_sclk_o <= '0';
    ljd_dac_main_data_o <= '0'; lj_dac_main_data_o <= '0';
    else else
    dac_main_sync_n_o <= '0'; dac_main_sync_n_o <= '0';
    dac_main_sclk_o <= '0'; dac_main_sclk_o <= '0';
    dac_main_data_o <= '0'; dac_main_data_o <= '0';
    ljd_dac_main_sync_n_o <= dac_main_sync_n; lj_dac_main_sync_n_o <= dac_main_sync_n;
    ljd_dac_main_sclk_o <= dac_main_sclk; lj_dac_main_sclk_o <= dac_main_sclk;
    ljd_dac_main_data_o <= dac_main_data; lj_dac_main_data_o <= dac_main_data;
    end if; end if;
    end process; end process;
    ......
    top/bare_top/scb_top_sim.vhd
    View file @ a155acb2
    ...@@ -226,10 +226,10 @@ begin -- rtl ...@@ -226,10 +226,10 @@ begin -- rtl
    i2c_sda_oen_o => i2c_sda_oen, i2c_sda_oen_o => i2c_sda_oen,
    i2c_sda_o => i2c_sda_out, i2c_sda_o => i2c_sda_out,
    i2c_sda_i => i2c_sda_in, i2c_sda_i => i2c_sda_in,
    ljd_loopback_i => '0', lj_loopback_i => '0',
    ljd_osc_freq_i => (others=>'0'), lj_osc_freq_i => (others=>'0'),
    ljd_pll_miso_i => '0', lj_pll_miso_i => '0',
    ljd_pll_locked_i=> '0' lj_pll_locked_i=> '0'
    ); );
    gen_phys : for i in 0 to g_num_ports-1 generate gen_phys : for i in 0 to g_num_ports-1 generate
    ......
    top/bare_top/wrsw_components_pkg.vhd
    View file @ a155acb2
    ...@@ -254,19 +254,19 @@ package wrsw_components_pkg is ...@@ -254,19 +254,19 @@ package wrsw_components_pkg is
    pll_cs_n_o : out std_logic; pll_cs_n_o : out std_logic;
    pll_sync_n_o : out std_logic; pll_sync_n_o : out std_logic;
    pll_reset_n_o : out std_logic; pll_reset_n_o : out std_logic;
    ljd_loopback_i : in std_logic; lj_loopback_i : in std_logic;
    ljd_loopback_o : out std_logic; lj_loopback_o : out std_logic;
    ljd_clk1_en : out std_logic; lj_clk1_en : out std_logic;
    ljd_clk2_en : out std_logic; lj_clk2_en : out std_logic;
    ljd_detected_o : out std_logic; lj_detected_o : out std_logic;
    ljd_osc_freq_i : in std_logic_vector (2 downto 0); lj_osc_freq_i : in std_logic_vector (2 downto 0);
    ljd_pll_mosi_o : out std_logic; lj_pll_mosi_o : out std_logic;
    ljd_pll_miso_i : in std_logic; lj_pll_miso_i : in std_logic;
    ljd_pll_sck_o : out std_logic; lj_pll_sck_o : out std_logic;
    ljd_pll_cs_n_o : out std_logic; lj_pll_cs_n_o : out std_logic;
    ljd_pll_sync_n_o : out std_logic; lj_pll_sync_n_o : out std_logic;
    ljd_pll_reset_n_o : out std_logic; lj_pll_reset_n_o : out std_logic;
    ljd_pll_locked_i : in std_logic); lj_pll_locked_i : in std_logic);
    end component; end component;
    component chipscope_icon component chipscope_icon
    ......
    top/bare_top/wrsw_top_pkg.vhd
    View file @ a155acb2
    ...@@ -296,19 +296,19 @@ package wrsw_top_pkg is ...@@ -296,19 +296,19 @@ package wrsw_top_pkg is
    pll_cs_n_o : out std_logic; pll_cs_n_o : out std_logic;
    pll_sync_n_o : out std_logic; pll_sync_n_o : out std_logic;
    pll_reset_n_o : out std_logic; pll_reset_n_o : out std_logic;
    ljd_loopback_i : in std_logic; lj_loopback_i : in std_logic;
    ljd_loopback_o : out std_logic; lj_loopback_o : out std_logic;
    ljd_clk1_en : out std_logic; lj_clk1_en : out std_logic;
    ljd_clk2_en : out std_logic; lj_clk2_en : out std_logic;
    ljd_detected_o : out std_logic; lj_detected_o : out std_logic;
    ljd_osc_freq_i : in std_logic_vector (2 downto 0); lj_osc_freq_i : in std_logic_vector (2 downto 0);
    ljd_pll_mosi_o : out std_logic; lj_pll_mosi_o : out std_logic;
    ljd_pll_miso_i : in std_logic; lj_pll_miso_i : in std_logic;
    ljd_pll_sck_o : out std_logic; lj_pll_sck_o : out std_logic;
    ljd_pll_cs_n_o : out std_logic; lj_pll_cs_n_o : out std_logic;
    ljd_pll_sync_n_o : out std_logic; lj_pll_sync_n_o : out std_logic;
    ljd_pll_reset_n_o : out std_logic; lj_pll_reset_n_o : out std_logic;
    ljd_pll_locked_i : in std_logic; lj_pll_locked_i : in std_logic;
    spll_dbg_o : out std_logic_vector(5 downto 0)); spll_dbg_o : out std_logic_vector(5 downto 0));
    end component; end component;
    ...@@ -362,23 +362,23 @@ package wrsw_top_pkg is ...@@ -362,23 +362,23 @@ package wrsw_top_pkg is
    dac_main_sync_n_o : out std_logic; dac_main_sync_n_o : out std_logic;
    dac_main_sclk_o : out std_logic; dac_main_sclk_o : out std_logic;
    dac_main_data_o : out std_logic; dac_main_data_o : out std_logic;
    ljd_dac_main_sync_n_o : out std_logic; lj_dac_main_sync_n_o : out std_logic;
    ljd_dac_main_sclk_o : out std_logic; lj_dac_main_sclk_o : out std_logic;
    ljd_dac_main_data_o : out std_logic; lj_dac_main_data_o : out std_logic;
    ljd_loopback_i : in std_logic; lj_loopback_i : in std_logic;
    ljd_loopback_o : out std_logic; lj_loopback_o : out std_logic;
    ljd_clk1_en : out std_logic; lj_clk1_en : out std_logic;
    ljd_clk2_en : out std_logic; lj_clk2_en : out std_logic;
    ljd_detected_o : out std_logic; lj_detected_o : out std_logic;
    ljd_present_o : out std_logic; lj_present_o : out std_logic;
    ljd_osc_freq_i : in std_logic_vector (2 downto 0); lj_osc_freq_i : in std_logic_vector (2 downto 0);
    ljd_pll_mosi_o : out std_logic; lj_pll_mosi_o : out std_logic;
    ljd_pll_miso_i : in std_logic; lj_pll_miso_i : in std_logic;
    ljd_pll_sck_o : out std_logic; lj_pll_sck_o : out std_logic;
    ljd_pll_cs_n_o : out std_logic; lj_pll_cs_n_o : out std_logic;
    ljd_pll_sync_n_o : out std_logic; lj_pll_sync_n_o : out std_logic;
    ljd_pll_reset_n_o : out std_logic; lj_pll_reset_n_o : out std_logic;
    ljd_pll_locked_i : in std_logic; lj_pll_locked_i : in std_logic;
    pll_status_i : in std_logic; pll_status_i : in std_logic;
    pll_mosi_o : out std_logic; pll_mosi_o : out std_logic;
    pll_miso_i : in std_logic; pll_miso_i : in std_logic;
    ......
    top/scb_18ports/scb_top_synthesis.ucf
    View file @ a155acb2
    ...@@ -22,26 +22,26 @@ NET "ext_clk_10mhz_n_i" LOC = AG30; ...@@ -22,26 +22,26 @@ NET "ext_clk_10mhz_n_i" LOC = AG30;
    INST "CLK_10MHZ_ext" LOC = BUFR_X0Y0; INST "CLK_10MHZ_ext" LOC = BUFR_X0Y0;
    INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1; INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1;
    NET "ljd_clk_62mhz_p_i" LOC = AN33; NET "lj_clk_62mhz_p_i" LOC = AN33;
    NET "ljd_clk_62mhz_n_i" LOC = AN34; NET "lj_clk_62mhz_n_i" LOC = AN34;
    NET "ljd_rev_id_i[0]" LOC = AE29; NET "lj_rev_id_i[0]" LOC = AE29;
    NET "ljd_rev_id_i[1]" LOC = AE28; NET "lj_rev_id_i[1]" LOC = AE28;
    NET "ljd_rev_id_i[2]" LOC = AM32; NET "lj_rev_id_i[2]" LOC = AM32;
    NET "ljd_osc_freq_i[0]" LOC = AN32; NET "lj_osc_freq_i[0]" LOC = AN32;
    NET "ljd_osc_freq_i[0]" PULLUP; NET "lj_osc_freq_i[0]" PULLUP;
    NET "ljd_osc_freq_i[1]" LOC = AP33; NET "lj_osc_freq_i[1]" LOC = AP33;
    NET "ljd_osc_freq_i[1]" PULLUP; NET "lj_osc_freq_i[1]" PULLUP;
    NET "ljd_osc_freq_i[2]" LOC = AP32; NET "lj_osc_freq_i[2]" LOC = AP32;
    NET "ljd_osc_freq_i[2]" PULLUP; NET "lj_osc_freq_i[2]" PULLUP;
    NET "ljd_clk1_en" LOC = AL31; NET "lj_clk1_en" LOC = AL31;
    NET "ljd_clk2_en" LOC = AK31; NET "lj_clk2_en" LOC = AK31;
    NET "ljd_loopback_i" LOC = AM31; NET "lj_loopback_i" LOC = AM31;
    NET "ljd_loopback_o" LOC = AL30; NET "lj_loopback_o" LOC = AL30;
    NET "ljd_pll_locked_i" LOC = AH33; NET "lj_pll_locked_i" LOC = AH33;
    #EBI BUS #EBI BUS
    #NET "cpu_clk_i" LOC=""; #NET "cpu_clk_i" LOC="";
    ...@@ -122,9 +122,9 @@ NET "dac_main_sync_n_o" LOC="AM17"; ...@@ -122,9 +122,9 @@ NET "dac_main_sync_n_o" LOC="AM17";
    NET "dac_main_sclk_o" LOC="AN17"; NET "dac_main_sclk_o" LOC="AN17";
    NET "dac_main_data_o" LOC="AP17"; NET "dac_main_data_o" LOC="AP17";
    NET "ljd_dac_main_sync_n_o" LOC = AH32; NET "lj_dac_main_sync_n_o" LOC = AH32;
    NET "ljd_dac_main_sclk_o" LOC = AK32; NET "lj_dac_main_sclk_o" LOC = AK32;
    NET "ljd_dac_main_data_o" LOC = AK33; NET "lj_dac_main_data_o" LOC = AK33;
    NET "pll_cs_n_o" LOC="AK18"; NET "pll_cs_n_o" LOC="AK18";
    NET "pll_sck_o" LOC="AE16"; NET "pll_sck_o" LOC="AE16";
    ...@@ -134,13 +134,13 @@ NET "pll_reset_n_o" LOC="AL16"; ...@@ -134,13 +134,13 @@ NET "pll_reset_n_o" LOC="AL16";
    NET "pll_status_i" LOC="K13"; NET "pll_status_i" LOC="K13";
    NET "pll_sync_n_o" LOC="AG18"; NET "pll_sync_n_o" LOC="AG18";
    NET "ljd_pll_cs_n_o" LOC = AD27; NET "lj_pll_cs_n_o" LOC = AD27;
    NET "ljd_pll_sck_o" LOC = AD26; NET "lj_pll_sck_o" LOC = AD26;
    NET "ljd_pll_mosi_o" LOC = AE27; NET "lj_pll_mosi_o" LOC = AE27;
    NET "ljd_pll_miso_i" LOC = AF28; NET "lj_pll_miso_i" LOC = AF28;
    NET "ljd_pll_reset_n_o" LOC = AF29; NET "lj_pll_reset_n_o" LOC = AF29;
    NET "ljd_pll_status_i" LOC = AD25; NET "lj_pll_status_i" LOC = AD25;
    NET "ljd_pll_sync_n_o" LOC = AJ34; NET "lj_pll_sync_n_o" LOC = AJ34;
    NET "uart_txd_o" LOC="E11"; NET "uart_txd_o" LOC="E11";
    NET "uart_rxd_i" LOC="D11"; NET "uart_rxd_i" LOC="D11";
    ...@@ -338,10 +338,10 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%; ...@@ -338,10 +338,10 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
    NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i; NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
    TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%; TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
    NET "ljd_clk_62mhz_p_i" TNM_NET = "ljd_clk_62mhz_p_i"; NET "lj_clk_62mhz_p_i" TNM_NET = "lj_clk_62mhz_p_i";
    TIMESPEC TS_ljd_clk_62mhz_p_i = PERIOD "ljd_clk_62mhz_p_i" 16 ns HIGH 50 %; TIMESPEC TS_lj_clk_62mhz_p_i = PERIOD "lj_clk_62mhz_p_i" 16 ns HIGH 50 %;
    NET "ljd_clk_62mhz_n_i" TNM_NET = "ljd_clk_62mhz_n_i"; NET "lj_clk_62mhz_n_i" TNM_NET = "lj_clk_62mhz_n_i";
    TIMESPEC TS_ljd_clk_62mhz_n_i = PERIOD "ljd_clk_62mhz_n_i" 16 ns HIGH 50 %; TIMESPEC TS_lj_clk_62mhz_n_i = PERIOD "lj_clk_62mhz_n_i" 16 ns HIGH 50 %;
    NET "ext_clk_10mhz_p_i" TNM_NET = "ext_clk_10mhz_p_i"; NET "ext_clk_10mhz_p_i" TNM_NET = "ext_clk_10mhz_p_i";
    TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %; TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %;
    ......
    top/scb_18ports/scb_top_synthesis.vhd
    View file @ a155acb2
    ...@@ -131,33 +131,33 @@ entity scb_top_synthesis is ...@@ -131,33 +131,33 @@ entity scb_top_synthesis is
    uart_rxd_i : in std_logic; uart_rxd_i : in std_logic;
    ------------------------------------------------------------------------------- -------------------------------------------------------------------------------
    -- WRS Low Jitter board -- WRS Low Jitter Support
    ------------------------------------------------------------------------------- -------------------------------------------------------------------------------
    ext_clk_10mhz_p_i : in std_logic; ext_clk_10mhz_p_i : in std_logic;
    ext_clk_10mhz_n_i : in std_logic; ext_clk_10mhz_n_i : in std_logic;
    ljd_clk_62mhz_p_i : in std_logic; lj_clk_62mhz_p_i : in std_logic;
    ljd_clk_62mhz_n_i : in std_logic; lj_clk_62mhz_n_i : in std_logic;
    ljd_pll_status_i : in std_logic; lj_pll_status_i : in std_logic;
    ljd_pll_mosi_o : out std_logic; lj_pll_mosi_o : out std_logic;
    ljd_pll_miso_i : in std_logic; lj_pll_miso_i : in std_logic;
    ljd_pll_sck_o : out std_logic; lj_pll_sck_o : out std_logic;
    ljd_pll_cs_n_o : out std_logic; lj_pll_cs_n_o : out std_logic;
    ljd_pll_sync_n_o : out std_logic; lj_pll_sync_n_o : out std_logic;
    ljd_pll_reset_n_o : out std_logic; lj_pll_reset_n_o : out std_logic;
    ljd_pll_locked_i : in std_logic; lj_pll_locked_i : in std_logic;
    ljd_dac_main_sync_n_o : out std_logic; lj_dac_main_sync_n_o : out std_logic;
    ljd_dac_main_sclk_o : out std_logic; lj_dac_main_sclk_o : out std_logic;
    ljd_dac_main_data_o : out std_logic; lj_dac_main_data_o : out std_logic;
    ljd_loopback_i : in std_logic; lj_loopback_i : in std_logic;
    ljd_loopback_o : out std_logic; lj_loopback_o : out std_logic;
    ljd_clk1_en : out std_logic; lj_clk1_en : out std_logic;
    ljd_clk2_en : out std_logic; lj_clk2_en : out std_logic;
    ljd_osc_freq_i : in std_logic_vector (2 downto 0); lj_osc_freq_i : in std_logic_vector (2 downto 0);
    ljd_rev_id_i : in std_logic_vector (2 downto 0); lj_rev_id_i : in std_logic_vector (2 downto 0);
    ------------------------------------------------------------------------------- -------------------------------------------------------------------------------
    ...@@ -330,11 +330,11 @@ architecture Behavioral of scb_top_synthesis is ...@@ -330,11 +330,11 @@ architecture Behavioral of scb_top_synthesis is
    signal clk_ext_100 : std_logic; signal clk_ext_100 : std_logic;
    signal ext_pll_100_locked, ext_pll_62_locked : std_logic; signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
    signal clk_ext_mul_locked : std_logic; signal clk_ext_mul_locked : std_logic;
    signal ljd_detected : std_logic := '0'; signal lj_detected : std_logic := '0';
    signal ljd_present : std_logic := '0'; signal lj_present : std_logic := '0';
    signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic; signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic;
    signal ljd_clk_62mhz, ljd_clk_62mhz_bufr : std_logic; signal lj_clk_62mhz, lj_clk_62mhz_bufr : std_logic;
    component scb_top_bare component scb_top_bare
    generic ( generic (
    ...@@ -373,23 +373,23 @@ architecture Behavioral of scb_top_synthesis is ...@@ -373,23 +373,23 @@ architecture Behavioral of scb_top_synthesis is
    dac_main_sync_n_o : out std_logic; dac_main_sync_n_o : out std_logic;
    dac_main_sclk_o : out std_logic; dac_main_sclk_o : out std_logic;
    dac_main_data_o : out std_logic; dac_main_data_o : out std_logic;
    ljd_dac_main_sync_n_o : out std_logic; lj_dac_main_sync_n_o : out std_logic;
    ljd_dac_main_sclk_o : out std_logic; lj_dac_main_sclk_o : out std_logic;
    ljd_dac_main_data_o : out std_logic; lj_dac_main_data_o : out std_logic;
    ljd_loopback_i : in std_logic; lj_loopback_i : in std_logic;
    ljd_loopback_o : out std_logic; lj_loopback_o : out std_logic;
    ljd_clk1_en : out std_logic; lj_clk1_en : out std_logic;
    ljd_clk2_en : out std_logic; lj_clk2_en : out std_logic;
    ljd_detected_o : out std_logic; lj_detected_o : out std_logic;
    ljd_present_o : out std_logic; lj_present_o : out std_logic;
    ljd_osc_freq_i : in std_logic_vector (2 downto 0); lj_osc_freq_i : in std_logic_vector (2 downto 0);
    ljd_pll_mosi_o : out std_logic; lj_pll_mosi_o : out std_logic;
    ljd_pll_miso_i : in std_logic; lj_pll_miso_i : in std_logic;
    ljd_pll_sck_o : out std_logic; lj_pll_sck_o : out std_logic;
    ljd_pll_cs_n_o : out std_logic; lj_pll_cs_n_o : out std_logic;
    ljd_pll_sync_n_o : out std_logic; lj_pll_sync_n_o : out std_logic;
    ljd_pll_reset_n_o : out std_logic; lj_pll_reset_n_o : out std_logic;
    ljd_pll_locked_i : in std_logic; lj_pll_locked_i : in std_logic;
    pll_status_i : in std_logic; pll_status_i : in std_logic;
    pll_mosi_o : out std_logic; pll_mosi_o : out std_logic;
    pll_miso_i : in std_logic; pll_miso_i : in std_logic;
    ...@@ -586,21 +586,21 @@ begin ...@@ -586,21 +586,21 @@ begin
    I => fpga_clk_ref_p_i, I => fpga_clk_ref_p_i,
    IB => fpga_clk_ref_n_i); IB => fpga_clk_ref_n_i);
    U_Buf_ljd_clk_62mhz : IBUFGDS U_Buf_lj_clk_62mhz : IBUFGDS
    generic map ( generic map (
    DIFF_TERM => true, DIFF_TERM => true,
    IOSTANDARD => "LVDS_25") IOSTANDARD => "LVDS_25")
    port map ( port map (
    O => ljd_clk_62mhz, O => lj_clk_62mhz,
    I => ljd_clk_62mhz_p_i, I => lj_clk_62mhz_p_i,
    IB => ljd_clk_62mhz_n_i); IB => lj_clk_62mhz_n_i);
    U_Buf_ljd_clk_62mhz_bufr : BUFR U_Buf_lj_clk_62mhz_bufr : BUFR
    port map ( port map (
    CE => '1', CE => '1',
    CLR => '0', CLR => '0',
    I => ljd_clk_62mhz, I => lj_clk_62mhz,
    O => ljd_clk_62mhz_bufr); O => lj_clk_62mhz_bufr);
    U_Buf_ext_clk10mhz : IBUFDS U_Buf_ext_clk10mhz : IBUFDS
    generic map ( generic map (
    ...@@ -627,8 +627,8 @@ begin ...@@ -627,8 +627,8 @@ begin
    O => clk_10mhz, O => clk_10mhz,
    I0 => clk_ext, I0 => clk_ext,
    I1 => ext_clk_10MHz_bufr, I1 => ext_clk_10MHz_bufr,
    S1 => ljd_present, S1 => lj_present,
    S0 => NOT ljd_present); S0 => NOT lj_present);
    U_Buf_CLK_DMTD : IBUFGDS U_Buf_CLK_DMTD : IBUFGDS
    generic map ( generic map (
    ...@@ -684,7 +684,7 @@ begin ...@@ -684,7 +684,7 @@ begin
    clk_ext_i => clk_ext, clk_ext_i => clk_ext,
    clk_ext_100_o => clk_ext_100, clk_ext_100_o => clk_ext_100,
    rst_a_i => ext_pll_reset, rst_a_i => ext_pll_reset,
    powerdown_i => ljd_detected, powerdown_i => lj_detected,
    locked_o => ext_pll_100_locked); locked_o => ext_pll_100_locked);
    U_Ext_PLL2: ext_pll_100_to_62m U_Ext_PLL2: ext_pll_100_to_62m
    ...@@ -692,12 +692,12 @@ begin ...@@ -692,12 +692,12 @@ begin
    clk_ext_100_i => clk_ext_100, clk_ext_100_i => clk_ext_100,
    clk_ext_mul_o => clk_ext_mul, clk_ext_mul_o => clk_ext_mul,
    rst_a_i => ext_pll_reset, rst_a_i => ext_pll_reset,
    powerdown_i => ljd_detected, powerdown_i => lj_detected,
    locked_o => ext_pll_62_locked); locked_o => ext_pll_62_locked);
    clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked; clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
    clk_ext_mul_vec(0) <= clk_ext_mul; clk_ext_mul_vec(0) <= clk_ext_mul;
    clk_ext_mul_vec(1) <= ljd_clk_62mhz_bufr; clk_ext_mul_vec(1) <= lj_clk_62mhz_bufr;
    local_reset <= not sys_rst_n_i; local_reset <= not sys_rst_n_i;
    U_Extend_EXT_Reset: gc_extend_pulse U_Extend_EXT_Reset: gc_extend_pulse
    ...@@ -889,24 +889,24 @@ begin ...@@ -889,24 +889,24 @@ begin
    dac_main_sync_n_o => dac_main_sync_n_o, dac_main_sync_n_o => dac_main_sync_n_o,
    dac_main_sclk_o => dac_main_sclk_o, dac_main_sclk_o => dac_main_sclk_o,
    dac_main_data_o => dac_main_data_o, dac_main_data_o => dac_main_data_o,
    -- Low-jitter daughterboard support -- Low-jitter support
    ljd_dac_main_sync_n_o => ljd_dac_main_sync_n_o, lj_dac_main_sync_n_o => lj_dac_main_sync_n_o,
    ljd_dac_main_sclk_o => ljd_dac_main_sclk_o, lj_dac_main_sclk_o => lj_dac_main_sclk_o,
    ljd_dac_main_data_o => ljd_dac_main_data_o, lj_dac_main_data_o => lj_dac_main_data_o,
    ljd_loopback_i => ljd_loopback_i, lj_loopback_i => lj_loopback_i,
    ljd_loopback_o => ljd_loopback_o, lj_loopback_o => lj_loopback_o,
    ljd_clk1_en => ljd_clk1_en, lj_clk1_en => lj_clk1_en,
    ljd_clk2_en => ljd_clk2_en, lj_clk2_en => lj_clk2_en,
    ljd_detected_o => ljd_detected, lj_detected_o => lj_detected,
    ljd_present_o => ljd_present, lj_present_o => lj_present,
    ljd_osc_freq_i => ljd_osc_freq_i, lj_osc_freq_i => lj_osc_freq_i,
    ljd_pll_mosi_o => ljd_pll_mosi_o, lj_pll_mosi_o => lj_pll_mosi_o,
    ljd_pll_miso_i => ljd_pll_miso_i, lj_pll_miso_i => lj_pll_miso_i,
    ljd_pll_sck_o => ljd_pll_sck_o, lj_pll_sck_o => lj_pll_sck_o,
    ljd_pll_cs_n_o => ljd_pll_cs_n_o, lj_pll_cs_n_o => lj_pll_cs_n_o,
    ljd_pll_sync_n_o => ljd_pll_sync_n_o, lj_pll_sync_n_o => lj_pll_sync_n_o,
    ljd_pll_reset_n_o => ljd_pll_reset_n_o, lj_pll_reset_n_o => lj_pll_reset_n_o,
    ljd_pll_locked_i => ljd_pll_locked_i, lj_pll_locked_i => lj_pll_locked_i,
    pll_status_i => clk_10mhz, pll_status_i => clk_10mhz,
    pll_mosi_o => pll_mosi_o, pll_mosi_o => pll_mosi_o,
    ......
    top/scb_8ports/scb_top_synthesis.ucf
    View file @ a155acb2
    ...@@ -22,23 +22,23 @@ NET "ext_clk_10mhz_n_i" LOC = AG30; ...@@ -22,23 +22,23 @@ NET "ext_clk_10mhz_n_i" LOC = AG30;
    INST "CLK_10MHZ_ext" LOC = BUFR_X0Y0; INST "CLK_10MHZ_ext" LOC = BUFR_X0Y0;
    INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1; INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1;
    NET "ljd_clk_62mhz_p_i" LOC = AN33; NET "lj_clk_62mhz_p_i" LOC = AN33;
    NET "ljd_clk_62mhz_n_i" LOC = AN34; NET "lj_clk_62mhz_n_i" LOC = AN34;
    NET "ljd_rev_id_i[0]" LOC = AE29; NET "lj_rev_id_i[0]" LOC = AE29;
    NET "ljd_rev_id_i[1]" LOC = AE28; NET "lj_rev_id_i[1]" LOC = AE28;
    NET "ljd_rev_id_i[2]" LOC = AM32; NET "lj_rev_id_i[2]" LOC = AM32;
    NET "ljd_osc_freq_i[0]" LOC = AN32; NET "lj_osc_freq_i[0]" LOC = AN32;
    NET "ljd_osc_freq_i[1]" LOC = AP33; NET "lj_osc_freq_i[1]" LOC = AP33;
    NET "ljd_osc_freq_i[2]" LOC = AP32; NET "lj_osc_freq_i[2]" LOC = AP32;
    NET "ljd_clk1_en" LOC = AL31; NET "lj_clk1_en" LOC = AL31;
    NET "ljd_clk2_en" LOC = AK31; NET "lj_clk2_en" LOC = AK31;
    NET "ljd_loopback_i" LOC = AM31; NET "lj_loopback_i" LOC = AM31;
    NET "ljd_loopback_o" LOC = AL30; NET "lj_loopback_o" LOC = AL30;
    NET "ljd_pll_locked_i" LOC = AH33; NET "lj_pll_locked_i" LOC = AH33;
    #NET "dbg_clk_ext_o" LOC=AM33; #NET "dbg_clk_ext_o" LOC=AM33;
    #NET "spll_dbg_o<0>" LOC=AL33; #NET "spll_dbg_o<0>" LOC=AL33;
    ...@@ -127,9 +127,9 @@ NET "dac_main_sync_n_o" LOC="AM17"; ...@@ -127,9 +127,9 @@ NET "dac_main_sync_n_o" LOC="AM17";
    NET "dac_main_sclk_o" LOC="AN17"; NET "dac_main_sclk_o" LOC="AN17";
    NET "dac_main_data_o" LOC="AP17"; NET "dac_main_data_o" LOC="AP17";
    NET "ljd_dac_main_sync_n_o" LOC = AH32; NET "lj_dac_main_sync_n_o" LOC = AH32;
    NET "ljd_dac_main_sclk_o" LOC = AK32; NET "lj_dac_main_sclk_o" LOC = AK32;
    NET "ljd_dac_main_data_o" LOC = AK33; NET "lj_dac_main_data_o" LOC = AK33;
    NET "pll_cs_n_o" LOC="AK18"; NET "pll_cs_n_o" LOC="AK18";
    NET "pll_sck_o" LOC="AE16"; NET "pll_sck_o" LOC="AE16";
    ...@@ -139,13 +139,13 @@ NET "pll_reset_n_o" LOC="AL16"; ...@@ -139,13 +139,13 @@ NET "pll_reset_n_o" LOC="AL16";
    NET "pll_status_i" LOC="K13"; NET "pll_status_i" LOC="K13";
    NET "pll_sync_n_o" LOC="AG18"; NET "pll_sync_n_o" LOC="AG18";
    NET "ljd_pll_cs_n_o" LOC = AD27; NET "lj_pll_cs_n_o" LOC = AD27;
    NET "ljd_pll_sck_o" LOC = AD26; NET "lj_pll_sck_o" LOC = AD26;
    NET "ljd_pll_mosi_o" LOC = AE27; NET "lj_pll_mosi_o" LOC = AE27;
    NET "ljd_pll_miso_i" LOC = AF28; NET "lj_pll_miso_i" LOC = AF28;
    NET "ljd_pll_reset_n_o" LOC = AF29; NET "lj_pll_reset_n_o" LOC = AF29;
    NET "ljd_pll_status_i" LOC = AD25; NET "lj_pll_status_i" LOC = AD25;
    NET "ljd_pll_sync_n_o" LOC = AJ34; NET "lj_pll_sync_n_o" LOC = AJ34;
    NET "uart_txd_o" LOC="E11"; NET "uart_txd_o" LOC="E11";
    NET "uart_rxd_i" LOC="D11"; NET "uart_rxd_i" LOC="D11";
    ...@@ -329,10 +329,10 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%; ...@@ -329,10 +329,10 @@ TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
    NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i; NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
    TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%; TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
    NET "ljd_clk_62mhz_p_i" TNM_NET = "ljd_clk_62mhz_p_i"; NET "lj_clk_62mhz_p_i" TNM_NET = "lj_clk_62mhz_p_i";
    TIMESPEC TS_ljd_clk_62mhz_p_i = PERIOD "ljd_clk_62mhz_p_i" 16 ns HIGH 50 %; TIMESPEC TS_lj_clk_62mhz_p_i = PERIOD "lj_clk_62mhz_p_i" 16 ns HIGH 50 %;
    NET "ljd_clk_62mhz_n_i" TNM_NET = "ljd_clk_62mhz_n_i"; NET "lj_clk_62mhz_n_i" TNM_NET = "lj_clk_62mhz_n_i";
    TIMESPEC TS_ljd_clk_62mhz_n_i = PERIOD "ljd_clk_62mhz_n_i" 16 ns HIGH 50 %; TIMESPEC TS_lj_clk_62mhz_n_i = PERIOD "lj_clk_62mhz_n_i" 16 ns HIGH 50 %;
    NET "ext_clk_10mhz_p_i" TNM_NET = "ext_clk_10mhz_p_i"; NET "ext_clk_10mhz_p_i" TNM_NET = "ext_clk_10mhz_p_i";
    TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %; TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %;
    ...@@ -377,7 +377,7 @@ AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED; ...@@ -377,7 +377,7 @@ AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;
    #NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE; #NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
    #Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17 #Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17
    TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY; TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
    TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY; TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY;
    #Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2019/07/12 #Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2019/07/12
    NET "gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin; NET "gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin;
    ......
    top/scb_8ports/scb_top_synthesis.vhd
    View file @ a155acb2
    ...@@ -130,28 +130,28 @@ entity scb_top_synthesis is ...@@ -130,28 +130,28 @@ entity scb_top_synthesis is
    -- WRS Low Jitter board -- WRS Low Jitter board
    ext_clk_10mhz_p_i : in std_logic; ext_clk_10mhz_p_i : in std_logic;
    ext_clk_10mhz_n_i : in std_logic; ext_clk_10mhz_n_i : in std_logic;
    ljd_clk_62mhz_p_i : in std_logic; lj_clk_62mhz_p_i : in std_logic;
    ljd_clk_62mhz_n_i : in std_logic; lj_clk_62mhz_n_i : in std_logic;
    ljd_pll_status_i : in std_logic; lj_pll_status_i : in std_logic;
    ljd_pll_mosi_o : out std_logic; lj_pll_mosi_o : out std_logic;
    ljd_pll_miso_i : in std_logic; lj_pll_miso_i : in std_logic;
    ljd_pll_sck_o : out std_logic; lj_pll_sck_o : out std_logic;
    ljd_pll_cs_n_o : out std_logic; lj_pll_cs_n_o : out std_logic;
    ljd_pll_sync_n_o : out std_logic; lj_pll_sync_n_o : out std_logic;
    ljd_pll_reset_n_o : out std_logic; lj_pll_reset_n_o : out std_logic;
    ljd_pll_locked_i : in std_logic; lj_pll_locked_i : in std_logic;
    ljd_dac_main_sync_n_o : out std_logic; lj_dac_main_sync_n_o : out std_logic;
    ljd_dac_main_sclk_o : out std_logic; lj_dac_main_sclk_o : out std_logic;
    ljd_dac_main_data_o : out std_logic; lj_dac_main_data_o : out std_logic;
    ljd_loopback_i : in std_logic; lj_loopback_i : in std_logic;
    ljd_loopback_o : out std_logic; lj_loopback_o : out std_logic;
    ljd_clk1_en : out std_logic; lj_clk1_en : out std_logic;
    ljd_clk2_en : out std_logic; lj_clk2_en : out std_logic;
    ljd_osc_freq_i : in std_logic_vector (2 downto 0); lj_osc_freq_i : in std_logic_vector (2 downto 0);
    ljd_rev_id_i : in std_logic_vector (2 downto 0); lj_rev_id_i : in std_logic_vector (2 downto 0);
    uart_txd_o : out std_logic; uart_txd_o : out std_logic;
    ...@@ -330,9 +330,9 @@ architecture Behavioral of scb_top_synthesis is ...@@ -330,9 +330,9 @@ architecture Behavioral of scb_top_synthesis is
    signal ext_pll_100_locked, ext_pll_62_locked : std_logic; signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
    signal clk_ext_mul_locked : std_logic; signal clk_ext_mul_locked : std_logic;
    signal ljd_detected : std_logic := '0'; signal lj_detected : std_logic := '0';
    signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic; signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic;
    signal ljd_clk_62mhz, ljd_clk_62mhz_bufr : std_logic; signal lj_clk_62mhz, lj_clk_62mhz_bufr : std_logic;
    component scb_top_bare component scb_top_bare
    generic ( generic (
    ...@@ -371,22 +371,22 @@ architecture Behavioral of scb_top_synthesis is ...@@ -371,22 +371,22 @@ architecture Behavioral of scb_top_synthesis is
    dac_main_sync_n_o : out std_logic; dac_main_sync_n_o : out std_logic;
    dac_main_sclk_o : out std_logic; dac_main_sclk_o : out std_logic;
    dac_main_data_o : out std_logic; dac_main_data_o : out std_logic;
    ljd_dac_main_sync_n_o : out std_logic; lj_dac_main_sync_n_o : out std_logic;
    ljd_dac_main_sclk_o : out std_logic; lj_dac_main_sclk_o : out std_logic;
    ljd_dac_main_data_o : out std_logic; lj_dac_main_data_o : out std_logic;
    ljd_loopback_i : in std_logic; lj_loopback_i : in std_logic;
    ljd_loopback_o : out std_logic; lj_loopback_o : out std_logic;
    ljd_clk1_en : out std_logic; lj_clk1_en : out std_logic;
    ljd_clk2_en : out std_logic; lj_clk2_en : out std_logic;
    ljd_detected_o : out std_logic; lj_detected_o : out std_logic;
    ljd_osc_freq_i : in std_logic_vector (2 downto 0); lj_osc_freq_i : in std_logic_vector (2 downto 0);
    ljd_pll_mosi_o : out std_logic; lj_pll_mosi_o : out std_logic;
    ljd_pll_miso_i : in std_logic; lj_pll_miso_i : in std_logic;
    ljd_pll_sck_o : out std_logic; lj_pll_sck_o : out std_logic;
    ljd_pll_cs_n_o : out std_logic; lj_pll_cs_n_o : out std_logic;
    ljd_pll_sync_n_o : out std_logic; lj_pll_sync_n_o : out std_logic;
    ljd_pll_reset_n_o : out std_logic; lj_pll_reset_n_o : out std_logic;
    ljd_pll_locked_i : in std_logic; lj_pll_locked_i : in std_logic;
    pll_status_i : in std_logic; pll_status_i : in std_logic;
    pll_mosi_o : out std_logic; pll_mosi_o : out std_logic;
    pll_miso_i : in std_logic; pll_miso_i : in std_logic;
    ...@@ -520,21 +520,21 @@ begin ...@@ -520,21 +520,21 @@ begin
    I => fpga_clk_ref_p_i, I => fpga_clk_ref_p_i,
    IB => fpga_clk_ref_n_i); IB => fpga_clk_ref_n_i);
    U_Buf_ljd_clk_62mhz : IBUFGDS U_Buf_lj_clk_62mhz : IBUFGDS
    generic map ( generic map (
    DIFF_TERM => true, DIFF_TERM => true,
    IOSTANDARD => "LVDS_25") IOSTANDARD => "LVDS_25")
    port map ( port map (
    O => ljd_clk_62mhz, O => lj_clk_62mhz,
    I => ljd_clk_62mhz_p_i, I => lj_clk_62mhz_p_i,
    IB => ljd_clk_62mhz_n_i); IB => lj_clk_62mhz_n_i);
    U_Buf_ljd_clk_62mhz_bufr : BUFR U_Buf_lj_clk_62mhz_bufr : BUFR
    port map ( port map (
    CE => '1', CE => '1',
    CLR => '0', CLR => '0',
    I => ljd_clk_62mhz, I => lj_clk_62mhz,
    O => ljd_clk_62mhz_bufr); O => lj_clk_62mhz_bufr);
    U_Buf_ext_clk10mhz : IBUFDS U_Buf_ext_clk10mhz : IBUFDS
    generic map ( generic map (
    ...@@ -561,8 +561,8 @@ begin ...@@ -561,8 +561,8 @@ begin
    O => clk_10mhz, O => clk_10mhz,
    I0 => clk_ext, I0 => clk_ext,
    I1 => ext_clk_10MHz_bufr, I1 => ext_clk_10MHz_bufr,
    S1 => ljd_detected, S1 => lj_detected,
    S0 => NOT ljd_detected S0 => NOT lj_detected
    ); );
    U_Buf_CLK_DMTD : IBUFGDS U_Buf_CLK_DMTD : IBUFGDS
    ...@@ -619,7 +619,7 @@ begin ...@@ -619,7 +619,7 @@ begin
    clk_ext_i => clk_ext, clk_ext_i => clk_ext,
    clk_ext_100_o => clk_ext_100, clk_ext_100_o => clk_ext_100,
    rst_a_i => ext_pll_reset, rst_a_i => ext_pll_reset,
    powerdown_i => ljd_detected, powerdown_i => lj_detected,
    locked_o => ext_pll_100_locked); locked_o => ext_pll_100_locked);
    U_Ext_PLL2: ext_pll_100_to_62m U_Ext_PLL2: ext_pll_100_to_62m
    ...@@ -627,12 +627,12 @@ begin ...@@ -627,12 +627,12 @@ begin
    clk_ext_100_i => clk_ext_100, clk_ext_100_i => clk_ext_100,
    clk_ext_mul_o => clk_ext_mul, clk_ext_mul_o => clk_ext_mul,
    rst_a_i => ext_pll_reset, rst_a_i => ext_pll_reset,
    powerdown_i => ljd_detected, powerdown_i => lj_detected,
    locked_o => ext_pll_62_locked); locked_o => ext_pll_62_locked);
    clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked; clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
    clk_ext_mul_vec(0) <= clk_ext_mul; clk_ext_mul_vec(0) <= clk_ext_mul;
    clk_ext_mul_vec(1) <= ljd_clk_62mhz_bufr; clk_ext_mul_vec(1) <= lj_clk_62mhz_bufr;
    --dbg_clk_ext_o <= clk_ext_mul; --dbg_clk_ext_o <= clk_ext_mul;
    local_reset <= not sys_rst_n_i; local_reset <= not sys_rst_n_i;
    ...@@ -825,22 +825,22 @@ begin ...@@ -825,22 +825,22 @@ begin
    dac_main_sclk_o => dac_main_sclk_o, dac_main_sclk_o => dac_main_sclk_o,
    dac_main_data_o => dac_main_data_o, dac_main_data_o => dac_main_data_o,
    -- Low-jitter daughterboard support -- Low-jitter daughterboard support
    ljd_dac_main_sync_n_o => ljd_dac_main_sync_n_o, lj_dac_main_sync_n_o => lj_dac_main_sync_n_o,
    ljd_dac_main_sclk_o => ljd_dac_main_sclk_o, lj_dac_main_sclk_o => lj_dac_main_sclk_o,
    ljd_dac_main_data_o => ljd_dac_main_data_o, lj_dac_main_data_o => lj_dac_main_data_o,
    ljd_loopback_i => ljd_loopback_i, lj_loopback_i => lj_loopback_i,
    ljd_loopback_o => ljd_loopback_o, lj_loopback_o => lj_loopback_o,
    ljd_clk1_en => ljd_clk1_en, lj_clk1_en => lj_clk1_en,
    ljd_clk2_en => ljd_clk2_en, lj_clk2_en => lj_clk2_en,
    ljd_detected_o => ljd_detected, lj_detected_o => lj_detected,
    ljd_osc_freq_i => ljd_osc_freq_i, lj_osc_freq_i => lj_osc_freq_i,
    ljd_pll_mosi_o => ljd_pll_mosi_o, lj_pll_mosi_o => lj_pll_mosi_o,
    ljd_pll_miso_i => ljd_pll_miso_i, lj_pll_miso_i => lj_pll_miso_i,
    ljd_pll_sck_o => ljd_pll_sck_o, lj_pll_sck_o => lj_pll_sck_o,
    ljd_pll_cs_n_o => ljd_pll_cs_n_o, lj_pll_cs_n_o => lj_pll_cs_n_o,
    ljd_pll_sync_n_o => ljd_pll_sync_n_o, lj_pll_sync_n_o => lj_pll_sync_n_o,
    ljd_pll_reset_n_o => ljd_pll_reset_n_o, lj_pll_reset_n_o => lj_pll_reset_n_o,
    ljd_pll_locked_i => ljd_pll_locked_i, lj_pll_locked_i => lj_pll_locked_i,
    pll_status_i => clk_10mhz, pll_status_i => clk_10mhz,
    pll_mosi_o => pll_mosi_o, pll_mosi_o => pll_mosi_o,
    ......
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