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White Rabbit Switch - Gateware
Commits
a4e16ff4
Commit
a4e16ff4
authored
Jan 19, 2012
by
Maciej Lipinski
Browse files
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Plain Diff
swcore: changed output_block to pipelined WB interface
parent
84ae29d8
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Showing
7 changed files
with
723 additions
and
155 deletions
+723
-155
Manifest.py
modules/wrsw_swcore/Manifest.py
+1
-0
swc_core.vhd
modules/wrsw_swcore/swc_core.vhd
+44
-25
swc_packet_mem_read_pump.vhd
modules/wrsw_swcore/swc_packet_mem_read_pump.vhd
+2
-1
swc_swcore_pkg.vhd
modules/wrsw_swcore/swc_swcore_pkg.vhd
+30
-0
xswc_core.vhd
modules/wrsw_swcore/xswc_core.vhd
+62
-51
xswc_output_block.vhd
modules/wrsw_swcore/xswc_output_block.vhd
+584
-0
wave.do
testbench/swcore/wave.do
+0
-78
No files found.
modules/wrsw_swcore/Manifest.py
View file @
a4e16ff4
...
...
@@ -29,4 +29,5 @@ files = [
"swc_prio_encoder.vhd"
,
"swc_rr_arbiter.vhd"
,
"xswc_core.vhd"
,
"xswc_output_block.vhd"
,
]
\ No newline at end of file
modules/wrsw_swcore/swc_core.vhd
View file @
a4e16ff4
...
...
@@ -47,9 +47,13 @@ use ieee.numeric_std.all;
library
work
;
use
work
.
swc_swcore_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
entity
swc_core
is
generic
(
g_swc_num_ports
:
integer
:
=
c_swc_num_ports
;
g_swc_prio_width
:
integer
:
=
c_swc_prio_width
);
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
...
...
@@ -72,18 +76,24 @@ entity swc_core is
-- Fabric I/F : output (goes to the Endpoint)
-------------------------------------------------------------------------------
rx_sof_p1_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_eof_p1_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_dreq_i
:
in
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_ctrl_o
:
out
std_logic_vector
(
c_swc_num_ports
*
c_swc_ctrl_width
-
1
downto
0
);
rx_data_o
:
out
std_logic_vector
(
c_swc_num_ports
*
c_swc_data_width
-
1
downto
0
);
rx_valid_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_bytesel_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_idle_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_rerror_p1_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_terror_p1_i
:
in
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_tabort_p1_i
:
in
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
-- rx_sof_p1_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
-- rx_eof_p1_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
-- rx_dreq_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
-- rx_ctrl_o : out std_logic_vector(c_swc_num_ports * c_swc_ctrl_width - 1 downto 0);
-- rx_data_o : out std_logic_vector(c_swc_num_ports * c_swc_data_width - 1 downto 0);
-- rx_valid_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
-- rx_bytesel_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
-- rx_idle_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
-- rx_rerror_p1_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
-- rx_terror_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
-- rx_tabort_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
-------------------------------------------------------------------------------
-- pWB : output (goes to the Endpoint)
-------------------------------------------------------------------------------
src_i
:
in
t_wrf_source_in_array
(
g_swc_num_ports
-1
downto
0
);
src_o
:
out
t_wrf_source_out_array
(
g_swc_num_ports
-1
downto
0
);
-------------------------------------------------------------------------------
-- I/F with Routing Table Unit (RTU)
...
...
@@ -249,7 +259,7 @@ architecture rtl of swc_core is
gen_blocks
:
for
i
in
0
to
c_swc_num_ports
-1
generate
INPUT_BLOCK
:
swc_input_block
INPUT_BLOCK
:
swc_input_block
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n_i
,
...
...
@@ -265,6 +275,7 @@ architecture rtl of swc_core is
tx_dreq_o
=>
tx_dreq_o
(
i
),
tx_abort_p1_i
=>
tx_abort_p1_i
(
i
),
tx_rerror_p1_i
=>
tx_rerror_p1_i
(
i
),
-------------------------------------------------------------------------------
-- I/F with Page allocator (MMU)
-------------------------------------------------------------------------------
...
...
@@ -319,7 +330,8 @@ architecture rtl of swc_core is
);
OUTPUT_BLOCK
:
swc_output_block
-- OUTPUT_BLOCK: swc_output_block
OUTPUT_BLOCK
:
xswc_output_block
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n_i
,
...
...
@@ -352,17 +364,24 @@ architecture rtl of swc_core is
-------------------------------------------------------------------------------
-- Fabric I/F
-------------------------------------------------------------------------------
rx_sof_p1_o
=>
rx_sof_p1_o
(
i
),
rx_eof_p1_o
=>
rx_eof_p1_o
(
i
),
rx_dreq_i
=>
rx_dreq_i
(
i
),
rx_ctrl_o
=>
rx_ctrl_o
((
i
+
1
)
*
c_swc_ctrl_width
-1
downto
i
*
c_swc_ctrl_width
),
rx_data_o
=>
rx_data_o
((
i
+
1
)
*
c_swc_data_width
-1
downto
i
*
c_swc_data_width
),
rx_valid_o
=>
rx_valid_o
(
i
),
rx_bytesel_o
=>
rx_bytesel_o
(
i
),
rx_idle_o
=>
rx_idle_o
(
i
),
rx_rerror_p1_o
=>
rx_rerror_p1_o
(
i
),
rx_terror_p1_i
=>
rx_terror_p1_i
(
i
),
rx_tabort_p1_i
=>
rx_tabort_p1_i
(
i
)
-- rx_sof_p1_o => rx_sof_p1_o(i),
-- rx_eof_p1_o => rx_eof_p1_o(i),
-- rx_dreq_i => rx_dreq_i(i),
-- rx_ctrl_o => rx_ctrl_o((i + 1) * c_swc_ctrl_width -1 downto i * c_swc_ctrl_width),
-- rx_data_o => rx_data_o((i + 1) * c_swc_data_width -1 downto i * c_swc_data_width),
-- rx_valid_o => rx_valid_o(i),
-- rx_bytesel_o => rx_bytesel_o(i),
-- rx_idle_o => rx_idle_o(i),
-- rx_rerror_p1_o => rx_rerror_p1_o(i),
-- rx_terror_p1_i => rx_terror_p1_i(i),
-- rx_tabort_p1_i => rx_tabort_p1_i(i)
-------------------------------------------------------------------------------
-- pWB : output (goes to the Endpoint)
-------------------------------------------------------------------------------
src_i
=>
src_i
(
i
),
src_o
=>
src_o
(
i
)
);
end
generate
gen_blocks
;
...
...
modules/wrsw_swcore/swc_packet_mem_read_pump.vhd
View file @
a4e16ff4
...
...
@@ -345,7 +345,8 @@ begin -- syn
end
if
;
if
(
dreq_i
=
'1'
and
reg_not_empty
=
'1'
and
load_out_reg
=
'0'
)
then
-- if(dreq_i = '1' and reg_not_empty = '1' and load_out_reg = '0') then
if
(
reg_not_empty
=
'1'
and
load_out_reg
=
'0'
)
then
read_valid
<=
'1'
;
elsif
(
load_out_reg
=
'1'
and
pckend
=
'0'
)
then
read_valid
<=
'1'
;
...
...
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @
a4e16ff4
...
...
@@ -43,6 +43,9 @@ use ieee.std_logic_1164.all;
use
ieee
.
math_real
.
CEIL
;
use
ieee
.
math_real
.
log2
;
library
work
;
use
work
.
wr_fabric_pkg
.
all
;
package
swc_swcore_pkg
is
type
t_swcore_gen_parameters
is
record
...
...
@@ -433,6 +436,33 @@ package swc_swcore_pkg is
);
end
component
;
component
xswc_output_block
is
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
pta_transfer_data_valid_i
:
in
std_logic
;
pta_pageaddr_i
:
in
std_logic_vector
(
c_swc_page_addr_width
-
1
downto
0
);
pta_prio_i
:
in
std_logic_vector
(
c_swc_prio_width
-
1
downto
0
);
pta_pck_size_i
:
in
std_logic_vector
(
c_swc_max_pck_size_width
-
1
downto
0
);
pta_transfer_data_ack_o
:
out
std_logic
;
mpm_pgreq_o
:
out
std_logic
;
mpm_pgaddr_o
:
out
std_logic_vector
(
c_swc_page_addr_width
-
1
downto
0
);
mpm_pckend_i
:
in
std_logic
;
mpm_pgend_i
:
in
std_logic
;
mpm_drdy_i
:
in
std_logic
;
mpm_dreq_o
:
out
std_logic
;
mpm_data_i
:
in
std_logic_vector
(
c_swc_data_width
-
1
downto
0
);
mpm_ctrl_i
:
in
std_logic_vector
(
c_swc_ctrl_width
-
1
downto
0
);
mpm_sync_i
:
in
std_logic
;
ppfm_free_o
:
out
std_logic
;
ppfm_free_done_i
:
in
std_logic
;
ppfm_free_pgaddr_o
:
out
std_logic_vector
(
c_swc_page_addr_width
-
1
downto
0
);
src_i
:
in
t_wrf_source_in
;
src_o
:
out
t_wrf_source_out
);
end
component
;
component
swc_output_block
is
port
(
clk_i
:
in
std_logic
;
...
...
modules/wrsw_swcore/xswc_core.vhd
View file @
a4e16ff4
...
...
@@ -115,18 +115,24 @@ architecture rtl of xswc_core is
-- Fabric I/F : output (goes to the Endpoint)
-------------------------------------------------------------------------------
rx_sof_p1_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_eof_p1_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_dreq_i
:
in
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_ctrl_o
:
out
std_logic_vector
(
c_swc_num_ports
*
c_swc_ctrl_width
-
1
downto
0
);
rx_data_o
:
out
std_logic_vector
(
c_swc_num_ports
*
c_swc_data_width
-
1
downto
0
);
rx_valid_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_bytesel_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_idle_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_rerror_p1_o
:
out
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_terror_p1_i
:
in
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
rx_tabort_p1_i
:
in
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
--
rx_sof_p1_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
--
rx_eof_p1_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
--
rx_dreq_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
--
rx_ctrl_o : out std_logic_vector(c_swc_num_ports * c_swc_ctrl_width - 1 downto 0);
--
rx_data_o : out std_logic_vector(c_swc_num_ports * c_swc_data_width - 1 downto 0);
--
rx_valid_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
--
rx_bytesel_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
--
rx_idle_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
--
rx_rerror_p1_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
--
rx_terror_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
--
rx_tabort_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
-------------------------------------------------------------------------------
-- pWB : output (goes to the Endpoint)
-------------------------------------------------------------------------------
src_i
:
in
t_wrf_source_in_array
(
g_swc_num_ports
-1
downto
0
);
src_o
:
out
t_wrf_source_out_array
(
g_swc_num_ports
-1
downto
0
);
-------------------------------------------------------------------------------
-- I/F with Routing Table Unit (RTU)
...
...
@@ -201,17 +207,17 @@ architecture rtl of xswc_core is
signal
swc_snk_tabort_p1
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
signal
swc_src_sof_p1
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
signal
swc_src_eof_p1
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
signal
swc_src_dreq
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
signal
swc_src_ctrl
:
std_logic_vector
(
c_swc_num_ports
*
c_swc_ctrl_width
-
1
downto
0
);
signal
swc_src_data
:
std_logic_vector
(
c_swc_num_ports
*
c_swc_data_width
-
1
downto
0
);
signal
swc_src_valid
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
signal
swc_src_bytesel
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
signal
swc_src_idle
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
signal
swc_src_rerror_p1
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
signal
swc_src_terror_p1
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
signal
swc_src_tabort_p1
:
std_logic_vector
(
c_swc_num_ports
-
1
downto
0
);
--
signal swc_src_sof_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0);
--
signal swc_src_eof_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0);
--
signal swc_src_dreq : std_logic_vector(c_swc_num_ports - 1 downto 0);
--
signal swc_src_ctrl : std_logic_vector(c_swc_num_ports * c_swc_ctrl_width - 1 downto 0);
--
signal swc_src_data : std_logic_vector(c_swc_num_ports * c_swc_data_width - 1 downto 0);
--
signal swc_src_valid : std_logic_vector(c_swc_num_ports - 1 downto 0);
--
signal swc_src_bytesel : std_logic_vector(c_swc_num_ports - 1 downto 0);
--
signal swc_src_idle : std_logic_vector(c_swc_num_ports - 1 downto 0);
--
signal swc_src_rerror_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0);
--
signal swc_src_terror_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0);
--
signal swc_src_tabort_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0);
begin
...
...
@@ -219,6 +225,8 @@ begin
gen_port_connections
:
for
i
in
0
to
g_swc_num_ports
-1
generate
swc_snk_ctrl
((
i
+
1
)
*
c_swc_ctrl_width
-
1
downto
i
*
c_swc_ctrl_width
+
2
)
<=
(
others
=>
'0'
);
CONV_wb_to_wrf
:
xwb_fabric_sink
port
map
(
...
...
@@ -236,29 +244,29 @@ begin
dreq_i
=>
swc_snk_dreq
(
i
)
);
CONV_wrf_to_wb
:
xwb_fabric_source
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n_i
,
src_i
=>
src_i
(
i
),
src_o
=>
src_o
(
i
),
addr_i
=>
swc_src_ctrl
((
i
+
1
)
*
c_swc_ctrl_width
-
3
downto
i
*
c_swc_ctrl_width
),
data_i
=>
swc_src_data
((
i
+
1
)
*
c_swc_data_width
-
1
downto
i
*
c_swc_data_width
),
dvalid_i
=>
swc_src_valid
(
i
),
sof_i
=>
swc_src_sof_p1
(
i
),
eof_i
=>
swc_src_eof_p1
(
i
),
error_i
=>
swc_src_rerror_p1
(
i
),
bytesel_i
=>
swc_src_bytesel
(
i
),
dreq_o
=>
swc_src_dreq
(
i
)
);
--
CONV_wrf_to_wb: xwb_fabric_source
--
--
port map(
--
clk_i => clk_i,
--
rst_n_i => rst_n_i,
--
src_i => src_i(i),
--
src_o => src_o(i),
--
addr_i => swc_src_ctrl((i+1)*c_swc_ctrl_width - 3 downto i*c_swc_ctrl_width),
--
data_i => swc_src_data((i+1)*c_swc_data_width - 1 downto i*c_swc_data_width),
--
dvalid_i => swc_src_valid(i),
--
sof_i => swc_src_sof_p1(i),
--
eof_i => swc_src_eof_p1(i),
--
error_i => swc_src_rerror_p1(i),
--
bytesel_i => swc_src_bytesel(i),
--
dreq_o => swc_src_dreq(i)
--
);
end
generate
;
swc_snk_tabort_p1
<=
(
others
=>
'0'
);
swc_src_terror_p1
<=
(
others
=>
'0'
);
swc_src_tabort_p1
<=
(
others
=>
'0'
);
--
swc_src_terror_p1 <= (others => '0');
--
swc_src_tabort_p1 <= (others => '0');
U_swc_core
:
swc_core
port
map
(
...
...
@@ -277,17 +285,20 @@ begin
tx_rerror_p1_i
=>
swc_snk_rerror_p1
,
--this is swc_source (itput data)
rx_sof_p1_o
=>
swc_src_sof_p1
,
rx_eof_p1_o
=>
swc_src_eof_p1
,
rx_dreq_i
=>
swc_src_dreq
,
rx_ctrl_o
=>
swc_src_ctrl
,
rx_data_o
=>
swc_src_data
,
rx_valid_o
=>
swc_src_valid
,
rx_bytesel_o
=>
swc_src_bytesel
,
rx_idle_o
=>
open
,
rx_rerror_p1_o
=>
swc_src_rerror_p1
,
rx_terror_p1_i
=>
swc_src_terror_p1
,
-- fake
rx_tabort_p1_i
=>
swc_src_tabort_p1
,
-- fake
-- rx_sof_p1_o => swc_src_sof_p1,
-- rx_eof_p1_o => swc_src_eof_p1,
-- rx_dreq_i => swc_src_dreq,
-- rx_ctrl_o => swc_src_ctrl,
-- rx_data_o => swc_src_data,
-- rx_valid_o => swc_src_valid,
-- rx_bytesel_o => swc_src_bytesel,
-- rx_idle_o => open,
-- rx_rerror_p1_o => swc_src_rerror_p1,
-- rx_terror_p1_i => swc_src_terror_p1, -- fake
-- rx_tabort_p1_i => swc_src_tabort_p1, -- fake
src_i
=>
src_i
,
src_o
=>
src_o
,
rtu_rsp_valid_i
=>
rtu_rsp_valid_i
,
rtu_rsp_ack_o
=>
rtu_rsp_ack_o
,
...
...
modules/wrsw_swcore/xswc_output_block.vhd
0 → 100644
View file @
a4e16ff4
This diff is collapsed.
Click to expand it.
testbench/swcore/wave.do
deleted
100644 → 0
View file @
84ae29d8
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/cyc_prev
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/trans_index
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/first_transaction
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/settings
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/cyc_start
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/cyc_end
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/clk_i
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/rst_n_i
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/src_i
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/src_o
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/addr_i
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/data_i
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/dvalid_i
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/sof_i
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/eof_i
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/error_i
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/bytesel_i
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/dreq_o
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/q_valid
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/full
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/we
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/rd
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/fin
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/fout
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/pre_dvalid
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/pre_eof
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/pre_data
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/pre_addr
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/post_dvalid
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/post_eof
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/post_sof
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/gen_port_connections(0)/conv_wrf_to_wb/err_status
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/src_i
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/u_xswc_core/src_o
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/src_dat_0_o
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/src_adr_0_o
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/src_sel_0_o
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/src_cyc_0_o
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/src_stb_0_o
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/src_we_0_o
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/src_stall_0_i
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/src_ack_0_i
add wave -noupdate /main/DUT_xswcore_wrapper/DUT_xswc_core_7_ports_wrapper/src_err_0_i
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/g_addr_width
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/g_data_width
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/clk_i
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/rst_n_i
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/adr
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/dat_i
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/sel
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/dat_o
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/ack
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/stall
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/err
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/rty
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/cyc
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/stb
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/we
add wave -noupdate /main/DUT_xswcore_wrapper/snk_0/last_access_t
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {4406260 ps} 0}
configure wave -namecolwidth 421
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {31516355 ps}
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